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CY7C1381D-100AXC Datasheet(PDF) 3 Page - Cypress Semiconductor |
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CY7C1381D-100AXC Datasheet(HTML) 3 Page - Cypress Semiconductor |
3 / 37 page CY7C1381D CY7C1383D CY7C1383F Document Number: 38-05544 Rev. *P Page 3 of 37 Contents Pin Configurations ........................................................... 4 Pin Definitions .................................................................. 6 Functional Overview ........................................................ 7 Single Read Accesses ................................................ 7 Single Write Accesses Initiated by ADSP ................... 7 Single Write Accesses Initiated by ADSC ................... 7 Burst Sequences ......................................................... 8 Sleep Mode ................................................................. 8 Interleaved Burst Address Table ................................. 8 Linear Burst Address Table ......................................... 8 ZZ Mode Electrical Characteristics .............................. 8 Truth Table ........................................................................ 9 Truth Table for Read/Write ............................................ 10 Truth Table for Read/Write ............................................ 10 IEEE 1149.1 Serial Boundary Scan (JTAG) .................. 11 Disabling the JTAG Feature ...................................... 11 Test Access Port (TAP) ............................................. 11 PERFORMING A TAP RESET .................................. 11 TAP REGISTERS ...................................................... 11 TAP Instruction Set ................................................... 11 TAP Controller State Diagram ....................................... 13 TAP Controller Block Diagram ...................................... 14 TAP Timing ...................................................................... 15 TAP AC Switching Characteristics ............................... 15 3.3 V TAP AC Test Conditions ....................................... 16 3.3 V TAP AC Output Load Equivalent ......................... 16 2.5 V TAP AC Test Conditions ....................................... 16 2.5 V TAP AC Output Load Equivalent ......................... 16 TAP DC Electrical Characteristics and Operating Conditions ............................................. 16 Identification Register Definitions ................................ 17 Scan Register Sizes ....................................................... 17 Instruction Codes ........................................................... 17 Boundary Scan Order .................................................... 18 Maximum Ratings ........................................................... 19 Operating Range ............................................................. 19 Neutron Soft Error Immunity ......................................... 19 Electrical Characteristics ............................................... 19 Capacitance .................................................................... 20 Thermal Resistance ........................................................ 20 AC Test Loads and Waveforms ..................................... 21 Switching Characteristics .............................................. 22 Timing Diagrams ............................................................ 23 Ordering Information ...................................................... 27 Ordering Code Definitions ......................................... 27 Package Diagrams .......................................................... 28 Acronyms ........................................................................ 30 Document Conventions ................................................. 30 Units of Measure ....................................................... 30 Appendix: Silicon Errata Document for RAM9 (90-nm), 18-Mb (CY7C138*D) Synchronous & NoBL™ SRAMs ................................... 31 Part Numbers Affected .............................................. 31 Product Status ........................................................... 31 Ram9 Sync/NoBL ZZ Pin, JTAG & Chip Enable Issues Errata Summary .................. 31 Document History Page ................................................. 34 Sales, Solutions, and Legal Information ...................... 37 Worldwide Sales and Design Support ....................... 37 Products .................................................................... 37 PSoC Solutions ......................................................... 37 |
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