CY7C1472V25 datasheet(11/39 Pages) CYPRESS

Part #	CY7C1472V25

Description	72-Mbit (2 M × 36/4 M × 18/1 M × 72) Pipelined SRAM with NoBL™ Architecture

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Manufacturer	CYPRESS [Cypress Semiconductor]

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CY7C1470V25

CY7C1472V25

CY7C1474V25

Document Number: 38-05290 Rev. *R

Page 11 of 39

Single Write Accesses

Write accesses are initiated when the following conditions are

satisfied at clock rise: (1) CEN is asserted LOW, (2) CE1, CE2,

and CE3 are all asserted active, and (3) the write signal WE is

asserted LOW. The address presented to the address inputs is

loaded into the address register. The write signals are latched

into the control logic block.

On the subsequent clock rise the data lines are automatically

tri-stated regardless of the state of the OE input signal. This

allows the external logic to present the data on DQ and DQP

(DQa,b,c,d,e,f,g,h/DQPa,b,c,d,e,f,g,h

for

CY7C1474V25,

DQa,b,c,d/DQPa,b,c,d for CY7C1470V25 and DQa,b/DQPa,b for

CY7C1472V25). In addition, the address for the subsequent

access (read/write/deselect) is latched into the address register

(provided the appropriate control signals are asserted).

On the next clock rise the data presented to DQ and DQP

(DQa,b,c,d,e,f,g,h/DQPa,b,c,d,e,f,g,h

for

CY7C1474V25,

DQa,b,c,d/DQPa,b,c,d for CY7C1470V25 & DQa,b/DQPa,b for

CY7C1472V25) (or a subset for byte write operations, see Write

Cycle Description table for details) inputs is latched into the

device and the write is complete.

The data written during the write operation is controlled by BW

(BWa,b,c,d,e,f,g,h for CY7C1474V25, BWa,b,c,d for CY7C1470V25

and

BWa,b

for

CY7C1472V25)

signals.

The

CY7C1470V25/CY7C1472V25/CY7C1474V25 provides byte

write capability that is described in the Write Cycle Description

table. Asserting the write enable input (WE) with the selected

byte write select (BW) input will selectively write to only the

desired bytes. Bytes not selected during a byte write operation

will

remain

unaltered.

A

synchronous

self-timed

write

mechanism has been provided to simplify the write operations.

Byte write capability has been included in order to greatly simplify

read/modify/write sequences, which can be reduced to simple

byte write operations.

Because the CY7C1470V25/CY7C1472V25/CY7C1474V25 are

common I/O devices, data should not be driven into the device

while the outputs are active. The output enable (OE) can be

deasserted HIGH before presenting data to the DQ and DQP

(DQa,b,c,d,e,f,g,h/DQPa,b,c,d,e,f,g,h

for

CY7C1474V25,

DQa,b,c,d/DQPa,b,c,d for CY7C1470V25 and DQa,b/DQPa,b for

CY7C1472V25) inputs. Doing so will tri-state the output drivers.

As

a

safety

precaution,

DQ

and

DQP

(DQa,b,c,d,e,f,g,h/DQPa,b,c,d,e,f,g,h

for

CY7C1474V25,

DQa,b,c,d/DQPa,b,c,d for CY7C1470V25 and DQa,b/DQPa,b for

CY7C1472V25) are automatically tri-stated during the data

portion of a write cycle, regardless of the state of OE.

Burst Write Accesses

The

CY7C1470V25/CY7C1472V25/CY7C1474V25

has

an

on-chip burst counter that allows the user the ability to supply a

single address and conduct up to four write operations without

reasserting the address inputs. ADV/LD must be driven LOW in

order to load the initial address, as described in Single Write

Accesses on page 11. When ADV/LD is driven HIGH on the

subsequent clock rise, the chip enables (CE1, CE2, and CE3)

and WE inputs are ignored and the burst counter is incremented.

The correct BW (BWa,b,c,d,e,f,g,h for CY7C1474V25, BWa,b,c,d for

CY7C1470V25 and BWa,b for CY7C1472V25) inputs must be

driven in each cycle of the burst write in order to write the correct

bytes of data.

Sleep Mode

The ZZ input pin is an asynchronous input. Asserting ZZ places

the SRAM in a power conservation “sleep” mode. Two clock

cycles are required to enter into or exit from this “sleep” mode.

While in this mode, data integrity is guaranteed. Accesses

pending when entering the “sleep” mode are not considered valid

nor is the completion of the operation guaranteed. The device

must be deselected prior to entering the “sleep” mode. CE1, CE2,

and CE3, must remain inactive for the duration of tZZREC after the

ZZ input returns LOW.

Linear Burst Address Table

(MODE = GND)

First

Address

A1:A0

Second

Address

A1:A0

Third

Address

A1:A0

Fourth

Address

A1:A0

00

01

10

11

01

10

11

00

10

11

00

01

11

00

01

10

Interleaved Burst Address Table

(MODE = Floating or VDD)

First

Address

A1:A0

Second

Address

A1:A0

Third

Address

A1:A0

Fourth

Address

A1:A0

00

01

10

11

01

00

11

10

11

00

01

11

10

01

00

ZZ Mode Electrical Characteristics

Parameter

Description

Test Conditions

Min

Max

Unit

IDDZZ

Sleep mode standby current

ZZ

 V

DD 0.2 V

–

120

mA

tZZS

Device operation to ZZ

ZZ

 V

DD  0.2 V

–

2tCYC

ns

tZZREC

ZZ recovery time

ZZ

 0.2 V

2tCYC

–ns

tZZI

ZZ active to sleep current

This parameter is sampled

–

2tCYC

ns

tRZZI

ZZ Inactive to exit sleep current

This parameter is sampled

0

–

ns

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