CY7C1441AV33

Document Number: 38-05357 Rev. *K

Page 6 of 34

Pin Definitions

Name

I/O

Description

Input-

Synchronous

Address Inputs Used to Select One of the Address Locations. Sampled at the rising edge of the CLK

Input-

Synchronous

Byte Write Select Inputs, Active LOW. Qualified with BWE to conduct byte writes to the SRAM.

Sampled on the rising edge of CLK.

GW

Input-

Synchronous

Global Write Enable Input, Active LOW. When asserted LOW on the rising edge of CLK, a global write

CLK

Input-

Clock

Clock Input. Used to capture all synchronous inputs to the device. Also used to increment the burst

counter when ADV is asserted LOW, during a burst operation.

Input-

Synchronous

external address is loaded.

Input-

Synchronous

Input-

Synchronous

is sampled only when a new external address is loaded.

OE

Input-

Asynchronous

Output Enable, Asynchronous Input, Active LOW. Controls the direction of the I/O pins. When LOW,

the I/O pins behave as outputs. When deasserted HIGH, I/O pins are tri-stated, and act as input data

pins. OE is masked during the first clock of a read cycle when emerging from a deselected state.

ADV

Input-

Synchronous

Advance Input Signal, Sampled on the Rising Edge of CLK. When asserted, it automatically

increments the address in a burst cycle.

ADSP

Input-

Synchronous

Address Strobe from Processor, Sampled on the Rising Edge of CLK, Active LOW. When asserted

into the burst counter. When ADSP and ADSC are both asserted, only ADSP is recognized. ASDP is

ADSC

Input-

Synchronous

Address Strobe from Controller, Sampled on the Rising Edge of CLK, Active LOW. When asserted

into the burst counter. When ADSP and ADSC are both asserted, only ADSP is recognized.

BWE

Input-

Synchronous

Byte Write Enable Input, Active LOW. Sampled on the rising edge of CLK. This signal must be asserted

LOW to conduct a byte write.

ZZ

Input-

Asynchronous

ZZ “sleep” Input, Active HIGH. When asserted HIGH places the device in a non-time-critical “sleep”

condition with data integrity preserved. For normal operation, this pin must be LOW or left floating. ZZ

pin has an internal pull down.

I/O-

Synchronous

Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register that is triggered by the

rising edge of CLK. As outputs, they deliver the data contained in the memory location specified by the

addresses presented during the previous clock rise of the read cycle. The direction of the pins is controlled

in a tri-state condition.The outputs are automatically tri-stated during the data portion of a write sequence,

during the first clock when emerging from a deselected state, and when the device is deselected,

regardless of the state of OE.

I/O-

Synchronous

MODE

selects interleaved burst sequence. This is a strap pin and should remain static during device operation.

Mode Pin has an internal pull up.

Power Supply Power Supply Inputs to the Core of the Device.

I/O Power

Supply

Power Supply for the I/O Circuitry.

Ground

Ground for the Core of the Device.