CY7C1363D

Document Number: 001-86215 Rev. **

Page 6 of 22

Functional Overview

All synchronous inputs pass through input registers controlled by

the rising edge of the clock. Maximum access delay from the

The CY7C1363D supports secondary cache in systems using

either a linear or interleaved burst sequence. The interleaved

burst order supports Pentium and i486™ processors. The linear

burst sequence is suited for processors that use a linear burst

sequence. The burst order is user-selectable, and is determined

by sampling the MODE input. Accesses can be initiated with

either the processor address strobe (ADSP) or the controller

address strobe (ADSC). Address advancement through the

burst sequence is controlled by the ADV input. A two-bit on-chip

wraparound burst counter captures the first address in a burst

sequence and automatically increments the address for the rest

of the burst access.

Byte write operations are qualified with the byte write enable

(GW) overrides all byte write inputs and writes data to all four

bytes. All writes are simplified with on-chip synchronous

self-timed write circuitry.

asynchronous output enable (OE) provide for easy bank

HIGH.

Single Read Accesses

A single read access is initiated when the following conditions

asserted active and (2) ADSP or ADSC is asserted LOW (if the

access is initiated by ADSC, the write inputs must be deasserted

during this first cycle). The address presented to the address

inputs is latched into the address register and the burst

counter/control logic and presented to the memory core. If the

OE input is asserted LOW, the requested data will be available

Single Write Accesses Initiated by ADSP

This access is initiated when the following conditions are

and (2) ADSP is asserted LOW. The addresses presented are

loaded into the address register and the burst inputs (GW, BWE,

next clock rise, the appropriate data will be latched and written

into the device.Byte writes are allowed. All I/Os are tristated

during a byte write. Since this is a common I/O device, the

asynchronous OE input signal must be deasserted and the I/Os

must be tristated prior to the presentation of data to DQs. As a

safety precaution, the data lines are tristated once a write cycle

is detected, regardless of the state of OE.

I/O power

supply

Power supply for the I/O circuitry.

Ground

Ground for the core of the device.

I/O ground

Ground for the I/O circuitry.

NC

–

No connects. Not internally connected to the die. 18M, 36M, 72M, 144M, 288M, 576M, and 1G are

address expansion pins and are not internally connected to the die.

Ground/DNU This pin can be connected to ground or should be left floating.

Name

I/O

Description

Note