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CY7C1327G Datasheet(PDF) 7 Page - Cypress Semiconductor

Part # CY7C1327G
Description  4-Mbit (256 K x 18) Pipelined Sync SRAM
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Manufacturer  CYPRESS [Cypress Semiconductor]
Direct Link  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

CY7C1327G Datasheet(HTML) 7 Page - Cypress Semiconductor

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CY7C1327G
Document Number: 38-05519 Rev. *M
Page 7 of 23
Truth Table
The Truth Table for CY7C1327G follows. [3, 4, 5, 6, 7]
Next Cycle
Add. Used
CE1 CE2 CE3 ZZ ADSP ADSC ADV
OE
DQ
WRITE
Unselected
None
H
X
X
L
X
L
X
X
Tri-state
X
Unselected
None
L
X
H
L
L
X
X
X
Tri-state
X
Unselected
None
L
L
X
L
L
X
X
X
Tri-state
X
Unselected
None
L
X
H
L
H
L
X
X
Tri-state
X
Unselected
None
L
L
X
L
H
L
X
X
Tri-state
X
Begin read
External
L
H
L
L
L
X
X
X
Tri-state
X
Begin read
External
L
H
L
L
H
L
X
X
Tri-state
H
Continue read
Next
X
X
X
L
H
H
L
H
Tri-state
H
Continue read
Next
X
X
X
L
H
H
L
L
DQ
H
Continue read
Next
H
X
X
L
X
H
L
H
Tri-state
H
Continue read
Next
H
X
X
L
X
H
L
L
DQ
H
Suspend read
Current
X
X
X
L
HHHH
Tri-state
H
Suspend read
Current
X
X
X
L
H
H
H
L
DQ
H
Suspend read
Current
H
X
X
L
X
H
H
H
Tri-state
H
Suspend read
Current
H
X
X
L
X
H
H
L
DQ
H
Begin write
Current
X
X
X
L
H
H
H
X
Tri-state
L
Begin write
Current
H
X
X
L
X
H
H
X
Tri-state
L
Begin write
External
L
H
L
L
H
H
X
X
Tri-state
L
Continue write
Next
X
X
X
L
H
H
H
X
Tri-state
L
Continue write
Next
H
X
X
L
X
H
H
X
Tri-state
L
Suspend write
Current
X
X
X
L
H
H
H
X
Tri-state
L
Suspend write
Current
H
X
X
L
X
H
H
X
Tri-state
L
ZZ “sleep”
None
X
X
X
H
XXXX
Tri-state
X
Notes
3. X = “Don't Care.” H = Logic HIGH, L = Logic LOW.
4. WRITE = L when any one or more byte write enable signals (BWA, BWB) and BWE = L or GW = L. WRITE = H when all byte write enable signals (BWA, BWB), BWE,
GW = H.
5. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.
6. The SRAM always initiates a read cycle when ADSP is asserted, regardless of the state of GW, BWE, or BW[A: B]. Writes may occur only on subsequent clocks after
the ADSP or with the assertion of ADSC. As a result, OE must be driven HIGH prior to the start of the write cycle to allow the outputs to tristate. OE is a don't care for
the remainder of the write cycle.
7. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle all data bits are tristate when OE is inactive
or when the device is deselected, and all data bits behave as output when OE is active (LOW).


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