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CY7C1325H-133AXI Datasheet(PDF) 9 Page - Cypress Semiconductor |
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CY7C1325H-133AXI Datasheet(HTML) 9 Page - Cypress Semiconductor |
9 / 21 page CY7C1325H Document Number: 001-86114 Rev. ** Page 9 of 21 Maximum Ratings Exceeding maximum ratings may shorten the useful life of the device. User guidelines are not tested. Storage temperature ................................ –65 °C to +150 °C Ambient temperature with power applied .......................................... –55 °C to +125 °C Supply voltage on VDD relative to GND .......–0.5 V to +4.6 V Supply voltage on VDDQ relative to GND ...... –0.5 V to +VDD DC voltage applied to outputs in tristate ...........................................–0.5 V to VDDQ + 0.5 V DC input voltage ................................. –0.5 V to VDD + 0.5 V Current into outputs (LOW) ........................................ 20 mA Static discharge voltage (per MIL-STD-883, method 3015) .......................... > 2001 V Latch-up current .................................................... > 200 mA Operating Range Range Ambient Temperature VDD VDDQ Industrial -40 °C to +85 °C 3.3 V 5% / + 10% 2.5 V – 5% to VDD Neutron Soft Error Immunity Parameter Description Test Conditions Typ Max* Unit LSBU Logical single bit upsets 25 °C 361 394 FIT/ Mb LMBU Logical multi bit upsets 25 °C 0 0.01 FIT/ Mb SEL Single event latch up 85 °C 0 0.1 FIT/ Dev * No LMBU or SEL events occurred during testing; this column represents a statistical 2, 95% confidence limit calculation. For more details refer to Application Note AN54908 “Accelerated Neutron SER Testing and Calculation of Terrestrial Failure Rates”. Electrical Characteristics Over the Operating Range Parameter [7, 8] Description Test Conditions Min Max Unit VDD Power supply voltage 3.135 3.6 V VDDQ I/O supply voltage 2.375 VDD V VOH Output HIGH voltage for 3.3 V I/O, IOH = –4.0 mA 2.4 – V for 2.5 V I/O, IOH = –1.0 mA 2.0 – V VOL Output LOW voltage for 3.3 V I/O, IOL = 8.0 mA – 0.4 V for 2.5 V I/O, IOL = 1.0 mA – 0.4 V VIH Input HIGH voltage for 3.3 V I/O 2.0 VDD + 0.3 V for 2.5 V I/O 1.7 VDD + 0.3 V VIL Input LOW voltage[7] for 3.3 V I/O –0.3 0.8 V for 2.5 V I/O –0.3 0.7 V IX Input leakage current except ZZ and MODE GND VI VDDQ 55 A Input current of MODE Input = VSS –30 – A Input = VDD –5 A Input current of ZZ Input = VSS –5 – A Input = VDD –30 A IOZ Output leakage current GND VI VDDQ, output disabled –5 5 A IDD VDD operating supply current VDD = Max, IOUT = 0 mA, f = fMAX= 1/tCYC 7.5 ns cycle, 133 MHz –225 mA Notes 7. Overshoot: VIH(AC) < VDD + 1.5 V (Pulse width less than tCYC/2), undershoot: VIL(AC) > –2 V (Pulse width less than tCYC/2). 8. Tpower up: Assumes a linear ramp from 0 V to VDD(min) within 200 ms. During this time VIH < VDD and VDDQ < VDD. |
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