CY7C131E, CY7C131AE

CY7C136E, CY7C136AE

Document Number: 001-64231 Rev. *E

Page 8 of 20

Switching Characteristics

Over the Operating Range

Parameter

Description

7C131E-55

7C136E-55

7C136AE-55

Unit

Min

Max

Read Cycle

Read cycle time

55

–

ns

Address to data valid [21]

–55

ns

Data hold from Address change

3

–

ns

CE LOW to data valid [21]

–55

ns

OE LOW to data valid [21]

–25

ns

OE LOW to Low Z [21, 22, 23]

3–

ns

OE HIGH to High Z [21, 22, 23]

–25

ns

CE LOW to Low Z [21, 22, 23]

5–

ns

CE HIGH to High Z [21, 22, 23]

–25

ns

CE LOW to power-up [22]

0–

ns

CE HIGH to power-down [22]

–35

ns

Write Cycle

Write cycle time

55

–

ns

CE LOW to write end

40

–

ns

Address setup to write end

40

–

ns

Address hold from write end

2

–

ns

Address setup to write start

0

–

ns

R/W pulse width

30

–

ns

Data setup to write end

20

–

ns

Data hold from write end

0

–

ns

R/W LOW to High Z [24]

–25

ns

R/W HIGH to Low Z [24]

3–

ns

Busy/Interrupt Timing[20]

BUSY LOW from Address match

–

30

ns

BUSY HIGH from Address mismatch [25]

–30

ns

BUSY LOW from CE LOW

–

30

ns

BUSY HIGH from CE HIGH [25]

–30

ns

Port setup for priority

5

–

ns

BUSY HIGH to valid data

–

45

ns

Notes

20. Test conditions used are Load 2.

21. The internal write time of the memory is defined by the overlap of CE LOW and R/W LOW. Both signals must be low to initiate a write and either signal can terminate

a write by going high. The data input setup and hold timing should be referenced to the rising edge of the signal that terminates the write.

23. These parameters are measured from the input signal changing, until the output pin goes to a high impedance state.

state voltage.

25. A write operation on Port A, where Port A has priority, leaves the data on Port B’s outputs undisturbed until one access time after one of the following:

BUSY on Port B goes HIGH.

Port B’s address toggled.

CE for Port B is toggled.

R/W for Port B is toggled during valid read.