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OMAP3530ECBCA Datasheet(PDF) 2 Page - Texas Instruments |
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OMAP3530ECBCA Datasheet(HTML) 2 Page - Texas Instruments |
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2 / 264 page  OMAP3530/25 Applications Processor SPRS507F – FEBRUARY 2008 – REVISED OCTOBER 2009 www.ti.com – 16K-Byte Data Cache (4-Way • Up to 24-Bit RGB Set-Associative) • HD Maximum Resolution – 256K-Byte L2 Cache • Supports Up to 2 LCD Panels • 112K-Byte ROM • Support for Remote Frame Buffer Interface (RFBI) LCD Panels • 64K-Byte Shared SRAM – 2 10-Bit Digital-to-Analog Converters • Endianess: (DACs) Supporting: – ARM Instructions - Little Endian • Composite NTSC/PAL Video – ARM Data – Configurable • Luma/Chroma Separate Video (S-Video) – DSP Instruction/Data - Little Endian – Rotation 90-, 180-, and 270-degrees • External Memory Interfaces: – Resize Images From 1/4x to 8x – SDRAM Controller (SDRC) – Color Space Converter • 16, 32-bit Memory Controller With – 8-bit Alpha Blending 1G-Byte Total Address Space • Serial Communication • Interfaces to Low-Power Double Data – 5 Multichannel Buffered Serial Ports Rate (LPDDR) SDRAM (McBSPs) • SDRAM Memory Scheduler (SMS) and • 512 Byte Transmit/Receive Buffer Rotation Engine (McBSP1/3/4/5) – General Purpose Memory Controller • 5K-Byte Transmit/Receive Buffer (GPMC) (McBSP2) • 16-bit Wide Multiplexed Address/Data • SIDETONE Core Support (McBSP2 and 3 Bus Only) For Filter, Gain, and Mix • Up to 8 Chip Select Pins With 128M-Byte Operations Address Space per Chip Select Pin • Direct Interface to I2S and PCM Device • Glueless Interface to NOR Flash, NAND and TDM Buses Flash (With ECC Hamming Code • 128 Channel Transmit/Receive Mode Calculation), SRAM and Pseudo-SRAM – Four Master/Slave Multichannel Serial Port • Flexible Asynchronous Protocol Control Interface (McSPI) Ports for Interface to Custom Logic (FPGA, – High-Speed/Full-Speed/Low-Speed USB CPLD, ASICs, etc.) OTG Subsystem (12-/8-Pin ULPI Interface) • Nonmultiplexed Address/Data Mode – High-Speed/Full-Speed/Low-Speed (Limited 2K-Byte Address Space) Multiport USB Host Subsystem • System Direct Memory Access (sDMA) • 12-/8-Pin ULPI Interface or 6-/4-/3-Pin Controller (32 Logical Channels With Serial Interface Configurable Priority) • Supports Transceiverless Link Logic • Camera Image Signal Processing (ISP) (TLL) – CCD and CMOS Imager Interface – One HDQ/1-Wire Interface – Memory Data Input – Three UARTs (One with Infrared Data – RAW Data Interface Association [IrDA] and Consumer Infrared – BT.601/BT.656 Digital YCbCr 4:2:2 [CIR] Modes) (8-/10-Bit) Interface – Three Master/Slave High-Speed – A-Law Compression and Decompression Inter-Integrated Circuit (I2C) Controllers – Preview Engine for Real-Time Image • Removable Media Interfaces: Processing – Three Multimedia Card (MMC)/ Secure – Glueless Interface to Common Video Digital (SD) With Secure Data I/O (SDIO) Decoders • Comprehensive Power, Reset, and Clock – Histogram Module/Auto-Exposure, Management Auto-White Balance, and Auto-Focus – SmartReflex™ Technology Engine – Dynamic Voltage and Frequency Scaling – Resize Engine (DVFS) • Resize Images From 1/4x to 4x • Test Interfaces • Separate Horizontal/Vertical Control – IEEE-1149.1 (JTAG) Boundary-Scan • Display Subsystem Compatible – Parallel Digital Output OMAP3530/25 Applications Processor CopyrightNote Submit Documentation Feedback |
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