4

UCC1921

UCC2921

UCC3921

Figure 1. Fault Timing Circuitry for the UCC3921, Including Power Limit Overload

APPLICATION INFORMATION

UDG-96275-1

SENSE: Input voltage from the current sense resistor.

When there is greater than 50mV across this pin with

charge.

SDFLTCH: This pin provides fault output indication,

shutdown

control,

and

operating

mode

selection.

Interface into and out of this pin is usually performed

through level shift transistors. When open, and under a

non-fault condition, this pin pulls to a low state with

respect to VSS. When a fault is detected by the fault

timer, or undervoltage lockout, this pin will drive to a high

state with respect fo VSS, indicating the NMOS pass

element is OFF. When > 250

µA is sourced into this pin

for > 1ms, it drives high causing the output to disable the

NMOS pass device.

Ω resistor is placed from this pin

to VSS, then the latched operating mode will be invoked.

Upon the occurrence of a fault, under the latched mode

the NMOS pass element latches off. A retry will not

periodically occur. To reset the latched off device, either

SDFLTCH is toggled high for a duration greater than 1ms

or the IC is powered down and then up.

VDD: Current driven with a resistor to a voltage approxi-

mately 10V more positive than VSS. Typically a resistor is

connected to ground. The 10V shunt regulator clamps

VDD approximately 10V above VSS, and is also used as

an output reference to program the maximum allowable

sourcing current.

VSS: Ground reference for the IC and the most negative

voltage available.

PIN DESCRIPTIONS (continued)