16-Bit ADC, 200ksps, 5V Single-Supply

with Reference

_______________________________________________________________________________________

5

Note 2: Relative accuracy is the deviation of the analog value at any code from its theoretical value after the gain error and offset

error have been nulled.

Note 3: Offset nulled.

Note 4: Conversion time is defined as the number of clock cycles multiplied by the clock period, clock has 50% duty cycle.

Includes the acquisition time.

Note 5: ADC performance is limited by the converter’s noise floor, typically 300µVp-p.

Note 6: When an external reference has a different voltage than the specified typical value, the full scale of the ADC will scale

proportionally.

this range, see the Typical Operating Characteristics. For guaranteed specifications beyond the limits, contact the factory.

Note 8: Defined as the change in positive full scale caused by a ±5% variation in the nominal supply voltage.

TIMING CHARACTERISTICS (Figures 5 and 6)

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

Acquisition Time

1.14

µs

DIN to SCLK Setup

50

ns

DIN to SCLK Hold

0ns

SCLK to DOUT Valid

70

ns

CS Fall to DOUT Enable

80

ns

CS Rise to DOUT Disable

80

ns

CS to SCLK Rise Setup

100

ns

CS to SCLK Rise Hold

0ns

SCLK High Pulse Width

80

ns

SCLK Low Pulse Width

80

ns

SCLK Fall to SSTRB

80

ns

CS Fall to SSTRB Enable

80

ns

CS Rise to SSTRB Disable

80

ns

SSTRB Rise to SCLK Rise

Internal clock mode

0

ns

RST Pulse Width

208

ns