Description

6

June 2006 Revised August 2011

SLLS690C

2.13 Terminal Assignments

The XIO1100 is packaged in a 100-pin GGB BGA package. See Section 6 for GGB-package terminal diagram.

Table 2−3 lists the terminal assignments in terminal-number order with corresponding signal names for the

GGB package.

Table 2−4 lists the terminal assignments arranged in alphanumerical order by signal name with corresponding

terminal numbers for the GGB package.

Table 2−3. 100-pin GGB Signal Name Sorted by Terminal Number

GGB

NUMBER

SIGNAL NAME

GGB

NUMBER

SIGNAL

NAME

GGB

NUMBER

SIGNAL NAME

GGB

NUMBER

SIGNAL NAME

A3

RX_DATA8

C9

RESERVED

G11

VSSA

L6

CLK_SEL

A4

RX_DATA9

C10

VSSA

G12

TXP

L7

VDD_IO

A5

RX_DATA11

C12

RXN

G13

TXN

L8

VSS

A6

RX_DATA13

C13

RXP

H1

TX_DATA13

L9

POWERDOWN1

A7

RX_DATA15

D1

RX_DATA4

H2

TX_DATA14

L10

DDR_EN

A8

RX_DATAK0

D2

RX_DATA5

H3

RX_VALID

L12

VDD_15_COMB

A9

RESERVED

D3

VSS

H11

VDD_33_COMB

L13

VDD_33_COM_IO

A10

RESERVED

D11

VDDA_33

H12

VDDA_15

M3

TX_DATA6

A11

REFCLK−

D12

VSSA

H13

VDDA_15

M4

TX_DATA5

B3

RX_ELECIDLE

D13

VSSA

J1

TX_DATA11

M5

TX_DATA3

B4

RX_DATA10

E1

RX_DATA2

J2

TX_DATA12

M6

TX_DATA1

B5

RX_DATA12

E2

RX_DATA3

J3

VSS

M7

TX_DATAK1

B6

RX_DATA14

E3

RX_STATUS0

J11

VSS

M8

TX_CLK

B7

RX_DATAK1

E11

VDDA_15

J12

VDDA_33

M9

POWERDOWN0

B8

RX_CLK

E12

VSSA

J13

VDDA_33

M10

P1_SLEEP

B9

RESERVED

E13

VDD_15

K1

TX_DATA9

M11

VREG_PD

B10

RESERVED

F1

RX_DATA0

K2

TX_DATA10

N3

TX_DATA7

B11

REFCLK+

F2

RX_DATA1

K3

VDD_IO

N4

TX_DATA4

C1

RX_DATA7

F3

VDD_IO

K11

VSSA

N5

TX_DATA2

C2

RX_DATA6

F11

VDD_15

K12

R0

N6

TX_DATA0

C4

VSS

F12

VSS

K13

R1

N7

TX_DATAK0

C5

VDD_IO

F13

VSSA

L1

TX_DATA8

N8

TXCOMPLIANCE

C6

RX_POLARITY

G1

RX_STATUS1

L2

VSS

N9

TXELECIDLE

C7

VDD_15_CORE

G2

TX_DATA15

L4

VDD_15_CORE

N10

PHY_STATUS

C8

VSS

G3

RX_STATUS2

L5

TXDETECTRX/L

OOPBACK

N11

RESETN