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MPC8536EEC Datasheet(PDF) 11 Page - Freescale Semiconductor, Inc |
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MPC8536EEC Datasheet(HTML) 11 Page - Freescale Semiconductor, Inc |
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11 / 126 page  Pin Assignments and Reset States MPC8536E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5 Freescale Semiconductor 11 LAD[0:31] Muxed data / address K22,L21,L22,K23,K24, L24,L25,K25,L28,L27, K28,K27,J28,H28,H27, G27,G26,F28,F26,F25, E28,E27,E26,F24,E24, C26,G24,E23,G23,F22, G22,G21 I/O BVDD 5,9,29 LDP[0:3] Data parity K26,G28,B27,E25 I/O BVDD 29 LA[27] Burst address L19 O BVDD 5,9,29 LA[28:31] Port address K16,K17,H17,G17 O BVDD 5,7,9,29 LCS[0:4] Chip selects K18,G19,H19,H20,G16 O BVDD 29 LCS5/DMA_DREQ2 Chips selects / DMA Request H16 I/O BVDD 1,29 LCS6/DMA_DACK2 Chips selects / DMA Ack J16 O BVDD 1,29 LCS7/DMA_DDONE2 Chips selects / DMA Done L18 O BVDD 1,29 LWE0/LBS0/LFWE Write enable / Byte select J22 O BVDD 5,9,29 LWE[1:3]/LBS[1:3] Write enable / Byte select H22,H23,H21 O BVDD 5,9,29 LBCTL Buffer control J25 O BVDD 5,8,9,29 LALE Address latch enable J26 O BVDD 5,8,9,29 LGPL0/LFCLE UPM general purpose line 0 / FLash command latch enable J20 O BVDD 5,9,29 LGPL1/LFALE UPM general purpose line 1 / Flash address latch enable K20 O BVDD 5,9,29 LGPL2/LOE/LFRE UPM general purpose line 2 / Output enable/Flash read enable G20 O BVDD 5,8,9,29 LGPL3/LFWP UPM general purpose line 3 / Flash write protect H18 O BVDD 5,9,29 LGPL4/LGTA/LUPWAIT /LPBSE/LFRB UPM general purpose line 4 / Target Ack/Wait/SDRAM parity byte select/Flash Ready-busy L20 I/O BVDD 29, 33 LGPL5 UPM general purpose line 5 / Amux K19 O BVDD 5,9,29 LCLK[0:2] Local bus clock H24,J24,H25 O BVDD 29 LSYNC_IN Synchronization D27 I BVDD 29 LSYNC_OUT Local bus DLL D28 O BVDD 29 DMA DMA_DACK[0:1] /GPIO[10:11] DMA Acknowledge AD6,AE10 O OVDD — Table 1. Pinout Listing (continued) Signal Signal Name Package Pin Number Pin Type Power Supply Notes |
Similar Part No. - MPC8536EEC |
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Similar Description - MPC8536EEC |
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