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MC68HC11F1CPU3 Datasheet(PDF) 9 Page - Freescale Semiconductor, Inc |
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MC68HC11F1CPU3 Datasheet(HTML) 9 Page - Freescale Semiconductor, Inc |
9 / 158 page TECHNICAL DATA Figure Title Page 1-1 MC68HC11F1 Block Diagram ........................................................................ 1-2 2-1 Pin Assignments for MC68HC11F1 68-Pin PLCC ......................................... 2-1 2-2 Pin Assignments for MC68HC11F1 80-Pin QFP ............................................ 2-2 2-3 External Reset Circuit ..................................................................................... 2-3 2-4 Common Crystal Connections ........................................................................ 2-4 2-5 External Oscillator Connections ..................................................................... 2-4 2-6 One Crystal Driving Two MCUs ..................................................................... 2-4 2-7 4XOUT Signal Driving a Second MCU ........................................................... 2-5 3-1 Programming Model ....................................................................................... 3-2 3-2 Stacking Operations ....................................................................................... 3-4 4-1 MC68HC11F1 Memory Map .......................................................................... 4-3 4-2 RAM Standby MODB/VSTBY Connections ..................................................... 4-4 4-3 Address Map for I/O and Program Chip Selects .......................................... 4-19 4-4 Address Map for General-Purpose Chip Select ........................................... 4-20 5-1 Processing Flow Out of Reset (1 of 2) ......................................................... 5-12 5-2 Processing Flow Out of Reset (2 of 2) ......................................................... 5-13 5-3 Interrupt Priority Resolution (1 of 2) ............................................................. 5-14 5-4 Interrupt Priority Resolution (2 of 2) ............................................................. 5-15 5-5 Interrupt Source Resolution Within SCI ........................................................ 5-16 7-1 SCI Transmitter Block Diagram ...................................................................... 7-2 7-2 SCI Receiver Block Diagram .......................................................................... 7-3 7-3 SCI Baud Rate Generator Block Diagram .................................................... 7-10 7-4 Interrupt Source Resolution Within SCI ........................................................ 7-12 8-1 SPI Block Diagram ......................................................................................... 8-2 8-2 SPI Transfer Format ....................................................................................... 8-3 9-1 Timer Clock Divider Chains ............................................................................ 9-2 9-2 Capture/Compare Block Diagram .................................................................. 9-4 9-3 Pulse Accumulator ....................................................................................... 9-16 10-1 A/D Converter Block Diagram ...................................................................... 10-2 10-2 Electrical Model of an A/D Input Pin (Sample Mode) ................................... 10-3 10-3 A/D Conversion Sequence ........................................................................... 10-4 A-1 Test Methods .................................................................................................. A-4 A-2 Timer Inputs ................................................................................................... A-5 A-3 POR External Reset Timing Diagram ............................................................. A-6 A-4 STOP Recovery Timing Diagram ................................................................... A-7 A-5 WAIT Recovery from Interrupt Timing Diagram ............................................. A-8 A-6 Interrupt Timing Diagram ................................................................................ A-9 A-7 Port Read Timing Diagram ........................................................................... A-10 A-8 Port Write Timing Diagram ........................................................................... A-10 A-9 Expansion Bus Timing .................................................................................. A-13 A-10 SPI Master Timing (CPHA = 0) .................................................................... A-15 LIST OF ILLUSTRATIONS Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com |
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