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XR16L2552IM-F Datasheet(PDF) 5 Page - Exar Corporation |
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XR16L2552IM-F Datasheet(HTML) 5 Page - Exar Corporation |
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5 / 45 page  XR16L2552 5 REV. 1.1.2 2.25V TO 5.5V DUART WITH 16-BYTE FIFO RIB# 27 31 I UART channel B Ring-Indicator (active low) or general purpose input. This input should be connected to VCC when not used. This input has no effect on the UART. MFA# 32 35 O Multi-Function Output Channel A. This output pin can function as the OP2A#, BAUDOUTA#, or RXRDYA# pin. One of these output signal functions can be selected by the user programmable bits 1-2 of the Alternate Function Register (AFR). These signal functions are described as follows: 1) OP2A# - When OP2A# (active low) is selected, the MF# pin is a logic 0 when MCR bit-3 is set to a logic 1 (see MCR bit-3). MCR bit-3 defaults to a logic 1 condition after a reset or power-up. 2) BAUDOUTA# - When BAUDOUTA# function is selected, the 16X Baud rate clock output is available at this pin. 3) RXRDYA# - RXRDYA# (active low) is intended for monitoring DMA data transfers. If using the 48-TQFP package, this output is already available at pin 31. If it is not used, leave it unconnected. MFB# 14 19 O Multi-Function Output ChannelB. This output pin can function as the OP2B#, BAUDOUTB#, or RXRDYB# pin. One of these output signal functions can be selected by the user programmable bits 1-2 of the Alternate Function Register (AFR). These signal functions are described as follows: 1) OP2B# - When OP2B# (active low) is selected, the MF# pin is a logic 0 when MCR bit-3 is set to a logic 1 (see MCR bit-3). MCR bit-3 defaults to a logic 1 condition after a reset or power-up. 2) BAUDOUTB# - When BAUDOUTB# function is selected, the 16X Baud rate clock output is available at this pin. 3) RXRDYB# - RXRDYB# (active low) is intended for monitoring DMA data transfers. If using the 48-TQFP package, this output is already available at pin 8. If it is not used, leave it unconnected. ANCILLARY SIGNALS XTAL1 5 11 I Crystal or external clock input. XTAL2 7 13 O Crystal or buffered clock output. RESET 16 21 I Reset (active high) - A longer than 40 ns logic 1 pulse on this pin will reset the internal registers and all outputs. The UART transmitter output will be held at logic 1, the receiver input will be ignored and outputs are reset during reset period (see External Reset Conditions). VCC 29, 42 44, 33 Pwr 2.25V to 5.5V power supply. All input pins are 5V tolerant. GND 6, 17 22, 12 Pwr Power supply common, ground. Pin Description NAME 48-TQFP PIN# 44-PLCC PIN # TYPE DESCRIPTION |
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