9

3.3V operation: Electrical Specifications

Test conditions that are not specified can be anywhere within the recommended operating range.

All typical specifications are at T

Parameter

Symbol

Min.

Typ.

Max.

Units Test Conditions

Quiescent Supply Current 1

I

DD1

mA

V

HCPL-9000/-0900

0.008

0.01

HCPL-9030/-0930

0.008

0.01

HCPL-9031/-0931

1.5

2.0

HCPL-900J/-090J

0.018

0.02

HCPL-901J/-091J

3.3

4.0

HCPL-902J/-092J

1.5

2.0

Quiescent Supply Current 2

I

DD2

mA

V

HCPL-9000/-0900

3.3

4.0

HCPL-9030/-0930

3.3

4.0

HCPL-9031/-0931

1.5

2.0

HCPL-900J/-090J

5.5

8.0

HCPL-901J/-091J

3.3

4.0

HCPL-902J/-092J

3.0

6.0

Logic Input Current

I

IN

-10

10

µA

Logic High Output Voltage

V

OH

V

V

DD2

V

I

0.8*V

DD2

V

V

I

Logic Low Output Voltage

V

OL

0

0.1

V

I

0.5

0.8

V

I

Switching Specifications

Maximum Data Rate

100

110

MBd

C

Clock Frequency

fmax

50

MHz

Propagation Delay Time to Logic

t

PHL

12

18

ns

Low Output

Propagation Delay Time toLogic

t

PLH

12

18

ns

High Output

Pulse Width

t

PW

10

ns

|PWD|

2

3

ns

|t

t

PSK

4

6

ns

Output Rise Time (10 – 90%)

t

R

2

4

ns

Output Fall Time (10 – 90%)

t

F

2

4

ns

Propagation Delay Enable to Output (Single Channel)

High to High Impedance

t

PHZ

3

5

ns

Low to High Impedance

t

PLZ

3

5

ns

High Impedance to High

t

PZH

3

5

ns

High Impedance to Low

t

PZL

3

5

ns

Channel-to-Channel Skew

t

CSK

2

3

ns

(Dual and Quad Channels)

Common Mode Transient Immunity |CM

15

18

kV/µs V

Notes:

1. PWD is defined as |t

2. t

3. CM

input voltage that can be sustained while maintaining V

voltage edges.

This product has been tested for electrostatic sensitivity to the limits stated in the specifications. However, Avago recommends that all integrated circuits

be handled with appropriate care to avoid damage. Damage caused by inappropriate handling or storage could range from performance degradation to

complete failure.