TPS54611, TPS54612

TPS54613, TPS54614

TPS54615, TPS54616

SLVS400C − AUGUST 2001 − REVISED APRIL 2005

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2

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during

storage or handling to prevent electrostatic damage to the MOS gates.

1

2

3

4

5

6

7

8

9

10

11

12

13

14

28

27

26

25

24

23

22

21

20

19

18

17

16

15

AGND

VSENSE

NC

PWRGD

BOOT

PH

PH

PH

PH

PH

PH

PH

PH

PH

RT

FSEL

SS/ENA

VBIAS

VIN

VIN

VIN

VIN

VIN

PGND

PGND

PGND

PGND

PGND

PWP PACKAGE

(TOP VIEW)

THERMAL

PAD

AVAILABLE OPTIONS

OUTPUT

PACKAGED DEVICES

OUTPUT

PACKAGED DEVICES

OUTPUT

VOLTAGE

PLASTIC HTSSOP

(PWP)(1)(2)

OUTPUT

VOLTAGE

PLASTIC HTSSOP

(PWP)(1)(2)

0.9 V

TPS54611PWP

1.8 V

TPS54614PWP

−40°C to 85°C

1.2 V

TPS54612PWP

−40°C to 85°C

2.5 V

TPS54615PWP

40 C to 85 C

1.5 V

TPS54613PWP

40 C to 85 C

3.3 V

TPS54616PWP

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of this data sheet for PowerPAD drawing and layout information.

Terminal Functions

TERMINAL

DESCRIPTION

NAME

NO.

DESCRIPTION

AGND

1

Analog ground. Return for slow-start capacitor, VBIAS capacitor, RT resistor FSEL. Make PowerPAD connection to AGND.

BOOT

5

Bootstrap input. 0.022-µF to 0.1-µF low-ESR capacitor connected from BOOT to PH generates floating drive for the

high-set FET driver.

NC

3

No connection

PGND

15−19 Power ground. High current return for the low-side driver and power MOSFET. Connect PGND with large copper areas to

the input and output supply returns, and negative terminals of the input and output capacitors.

PH

6−14

Phase input/output. Junction of the internal high-side and low-side power MOSFETs, and output inductor.

PWRGD

4

SS/ENA is low or internal shutdown signal active.

RT

28

Frequency setting resistor input. Connect a resistor from RT to AGND to set the switching frequency.

SS/ENA

26

Slow-start/enable input/output. Dual function pin which provides logic input to enable/disable device operation and

capacitor input to externally set the start-up time.

FSEL

27

Frequency select input. Provides logic input to select between two internally set switching frequencies.

VBIAS

25

Internal bias regulator output. Supplies regulated voltage to internal circuitry. Bypass VBIAS pin to AGND pin with a high

quality, low-ESR 0.1-µF to 1-µF ceramic capacitor.

VIN

20−24 Input supply for the power MOSFET switches and internal bias regulator. Bypass VIN pins to PGND pins close to device

package with a high quality, low-ESR 1-µF to 10-µF ceramic capacitor.

VSENSE

2

Error amplifier inverting input. Connect directly to output voltage sense point.