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TMS320DM8168CCYG Datasheet(PDF) 1 Page - Texas Instruments |
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TMS320DM8168CCYG Datasheet(HTML) 1 Page - Texas Instruments |
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1 / 327 page  TMS320DM8168, TMS320DM8167 TMS320DM8166, TMS320DM8165 www.ti.com SPRS614D – MARCH 2011 – REVISED JANUARY 2013 TMS320DM816x DaVinci Video Processors Check for Samples: TMS320DM8168, TMS320DM8167, TMS320DM8166, TMS320DM8165 1 Device Summary 1.1 Features 1234567891011 – 2 SP x SP → DP Every Two Clocks • High-Performance DaVinci™ Video Processors – 2 SP x DP → DP Every Three Clocks – ARM® Cortex™-A8 RISC Processor – 2 DP x DP → DP Every Four Clocks • Up to 1.35 GHz • Fixed-Point Multiply Supports Two 32 x – C674x VLIW DSP 32 Multiplies, Four 16 x 16-bit Multiplies • Up to 1.125 GHz including Complex Multiplies, or Eight 8 x • Up to 9000 MIPS and 6750 MFLOPS 8-Bit Multiplies per Clock Cycle • Fully Software-Compatible with C67x+™ • C674x Two-Level Memory Architecture and C64x+™ – 32K-Byte L1P and L1D RAM and Cache • ARM® Cortex™-A8 Core – 256K-Byte L2 Unified Mapped RAM and – ARMv7 Architecture Caches • In-Order, Dual-Issue, Superscalar • System Memory Management Unit (System Processor Core MMU) • NEON™ Multimedia Architecture – Maps C674x DSP and EMDA TCB Memory – Supports Integer and Floating Point (VFPv3- Accesses to System Addresses IEEE754 compliant) • 512K-Bytes On-Chip Memory Controller • Jazelle® RCT Execution Environment (OCMC) RAM • ARM® Cortex™-A8 Memory Architecture • Media Controller – 32K-Byte Instruction and Data Caches – Manages HDVPSS and HDVICP2 modules – 256K-Byte L2 Cache • Up to Three Programmable High-Definition – 64K-Byte RAM, 48K-Byte Boot ROM Video Image Coprocessing (HDVICP2) Engines • TMS320C674x Floating-Point VLIW DSP – Encode, Decode, Transcode Operations – 64 General-Purpose Registers (32-Bit) – H.264, MPEG2, VC1, MPEG4 SP and ASP – Six ALU (32-Bit and 40-Bit) Functional Units • SGX530 3D Graphics Engine (available only on • Supports 32-Bit Integer, SP (IEEE Single the DM8168 and DM8166 device) Precision, 32-Bit) and DP (IEEE Double – Delivers up to 30 MTriangles per second Precision, 64-Bit) Floating Point – Universal Scalable Shader Engine • Supports up to Four SP Adds Per Clock – Direct3D® Mobile, OpenGL® ES 1.1 and 2.0, and Four DP Adds Every Two Clocks OpenVG™ 1.1, OpenMax™ API Support • Supports up to Two Floating-Point (SP or – Advanced Geometry DMA Driven Operation DP) Approximate Reciprocal or Square – Programmable HQ Image Anti-Aliasing Root Operations Per Cycle • Endianness – Two Multiply Functional Units – ARM, DSP Instructions and Data – Little • Mixed-Precision IEEE Floating-Point Endian Multiply Supported up to: • HD Video Processing Subsystem (HDVPSS) – 2 SP x SP → SP Per Clock 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. 2 DaVinci, C64x+, SmartReflex, TMS320C6000, Code Composer Studio, DSP/BIOS, XDS are trademarks of Texas Instruments. 3 Cortex, NEON are trademarks of ARM Ltd or its subsidiaries. 4 ARM, Jazelle, Thumb are registered trademarks of ARM Ltd or its subsidiaries. 5 USSE, POWERVR are trademarks of Imagination Technologies Limited. 6 OpenVG, OpenMax are trademarks of Khronos Group Inc. 7 Direct3D, Microsoft, Windows are registered trademarks of Microsoft Corporation in the United States and/or other countries. 8 I2C BUS is a registered trademark of NXP B.V. Corporation Netherlands. 9 PCI Express, PCIe are registered trademarks of PCI-SIG. 10 OpenGL is a registered trademark of Silicon Graphics International Corp. or its subsidiaries in the United States and/or other countries. 11 All other trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to Copyright © 2011–2013, Texas Instruments Incorporated specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. |
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