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TMS320F241FNS Datasheet(PDF) 10 Page - Texas Instruments |
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TMS320F241FNS Datasheet(HTML) 10 Page - Texas Instruments |
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10 / 122 page  TMS320F243, TMS320F241 DSP CONTROLLERS SPRS064D − DECEMBER 1997 − REVISED FEBRUARY 2006 10 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 Terminal Functions - F243 PGE Package (Continued) NAME 144 LQFP TYPE† RESET STATE‡ DESCRIPTION NAME NO. TYPE† STATE‡ DESCRIPTION INTERRUPT, EXTERNAL ACCESS, AND MISCELLANEOUS SIGNALS (CONTINUED) IS 105 I/O, data, and program space strobe select signals. IS, DS, and PS are always high unless low-level asserted for access to the relevant external memory space or I/O. IS DS PS 105 110 107 O/Z 1 I/O, data, and program space strobe select signals. IS, DS, and PS are always high unless low-level asserted for access to the relevant external memory space or I/O. They are placed in the high-impedance state during reset, power down, and when DS PS 110 107 O/Z 1 They are placed in the high-impedance state during reset, power down, and when EMU1/OFF is active low. WE 112 O/Z 1 Write enable strobe. The falling edge of WE indicates that the device is driving the external data bus (D15 − D0). WE is active on all external program, data, and I/O writes. WE goes in the high-impedance state when EMU1/OFF is active low. RD 118 O/Z 1 Read enable strobe. Read-select indicates an active, external read cycle. RD is active on all external program, data, and I / O reads. RD goes into the high-impedance state when EMU1/OFF is active low. R/W 114 O/Z 1 Read/write signal. R/W indicates transfer direction during communication to an external device. It is normally in read mode (high), unless low level is asserted for performing a write operation. It is placed in the high-impedance state when EMU1/OFF is active low and during power down. STRB 122 O/Z 1 External memory access strobe. STRB is always high unless asserted low to indicate an external bus cycle. STRB is active for all off-chip accesses. It is placed in the high-impedance state during power down, and when EMU1/OFF is active low. BR 120 O/Z 1 Bus request, global memory strobe. BR is asserted during access of external global data memory space. BR can be used to extend the data memory address space by up to 32K words. BR goes in the high-impedance state during reset, power down, and when EMU1/OFF is active low. VIS_CLK 31 O 0 Visibility clock. Same as CLKOUT, but timing is aligned for external buses in visibility mode. ENA_144 18 I I Active high to enable external interface signals. If pulled low, the F243 behaves like an F241—i.e., it has no external memory and generates an illegal address if any of the three external spaces are accessed (IS, DS, PS asserted). This pin has an internal pulldown. ( ↓) VIS_OE 126 O 0 This pin is active (low) whenever the external databus is driving as an output during visibility mode. Can be used by external decode logic to prevent data bus contention while running in visibility mode. XF/IOPC0 49 I/O O − 1 External flag output (latched software-programmable signal). XF is a general-purpose output pin. It is set/reset by the SETC XF/CLRC XF instruction. This pin is configured as an external flag output by all device resets. It can be used as a GPIO, if not used as XF. BIO/IOPC1 55 I/O I Branch control input. BIO is polled by the BCND pma,BIO instruction. If BIO is low, a branch is executed. If BIO is not used, it should be pulled high. This pin is configured as a branch control input by all device resets. It can be used as a GPIO, if not used as a branch control input. † I = input, O = output, Z = high impedance ‡ The reset state indicates the state of the pin at reset. If the pin is an input, indicated by an I, its state is determined by user design. If the pin is an output, its level at reset is indicated. § At reset, the device comes up with AVIS mode enabled. The data bus is in output mode while AVIS is enabled. NOTE: Bold, italicized pin names indicate pin function after reset. LEGEND: ↑ − Internal pullup ↓ − Internal pulldown (Typical active pullup/pulldown value is 150 µA.) |
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