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TLV5638ID Datasheet(PDF) 6 Page - Texas Instruments |
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TLV5638ID Datasheet(HTML) 6 Page - Texas Instruments |
6 / 23 page www.ti.com ELECTRICAL CHARACTERISTICS (Continued) DIGITAL INPUT TIMING REQUIREMENTS PARAMETER MEASURMENT INFORMATION twL SCLK CS DIN D15 D14 D13 D12 D1 D0 X X 1 X 2 3 4 5 15 16 X twH tsu(D) th(D) tsu(CS-CK) tsu(C16-CS) TLV5638 SLAS225C – JUNE 1999 – REVISED JANUARY 2004 over recommended operating conditions, V ref = 2.048 V, Vref= 1.024 V (unless otherwise noted) ANALOG OUTPUT DYNAMIC PERFORMANCE PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Fast 1 3 ts(FS) Output settling time, full scale RL = 10 kΩ, CL = 100 pF, See(1) µs Slow 3.5 7 Fast 0.5 1.5 ts(CC) Output settling time, code to code RL = 10 kΩ, CL = 100 pF, See (2) µs Slow 1 2 Fast 12 SR Slew rate RL = 10 kΩ, CL = 100 pF, See (3) V/µs Slow 1.8 Glitch energy DIN = 0 to 1, FCLK = 100 kHz, CS = VDD 5 nV-s SNR Signal-to-noise ratio 69 74 S/(N+D) Signal-to-noise + distortion 58 67 fs = 480 kSPS, fout = 1 kHz, RL = 10 kΩ, dB CL = 100 pF THD Total harmonic distortion 69 57 Spurious free dynamic range 57 72 (1) Settling time is the time for the output signal to remain within ±0.5 LSB of the final measured value for a digital input code change of 0x020 to 0xFDF and 0xFDF to 0x020 respectively. Not tested, assured by design. (2) Settling time is the time for the output signal to remain within ± 0.5 LSB of the final measured value for a digital input code change of one count. Not tested, assured by design. (3) Slew rate determines the time it takes for a change of the DAC output from 10% to 90% full-scale voltage. MIN NOM MAX UNIT tsu(CS-CK) Setup time, CS low before first negative SCLK edge 10 ns tsu(C16-CS) Setup time, 16th negative SCLK edge (when D0 is sampled) before CS rising edge 10 ns twH SCLK pulse width high 25 ns twL SCLK pulse width low 25 ns tsu(D) Setup time, data ready before SCLK falling edge 10 ns th(D) Hold time, data held valid after SCLK falling edge 5 ns Figure 1. Timing Diagram 6 |
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