H27S4G6F2D datasheet(4/62 Pages) HYNIX

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H27S4G6F2D Datasheet(PDF) 4 Page - Hynix Semiconductor

Part #	H27S4G6F2D

Description	4 Gbit (512M x 8 bit) NAND Flash

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Manufacturer	HYNIX [Hynix Semiconductor]

Direct Link	http://www.skhynix.com/kor/main.do

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APCPCWM_4828539:WP_0000001WP_0000001

Rev 1.4 / OCT. 2010

H27(U_S)4G8_6F2D

4 Gbit (512M x 8 bit) NAND Flash

CONTENTS

1 Summary Description...................................................................................................................5

1.1 Product List....................................................................................................................................6

1.2 Pin description................................................................................................................................8

1.3 Functional block diagram...............................................................................................................9

1.4 Address role.................................................................................................................................10

1.5 Command Set...............................................................................................................................11

2 Bus Operations............................................................................................................................13

2.1 Command Input............................................................................................................................13

2.2 Address Input...............................................................................................................................13

2.3 Data Input....................................................................................................................................13

2.4 Data Output.................................................................................................................................13

2.5 Write Protect................................................................................................................................13

2.6 Stand-by......................................................................................................................................13

3 DEVICE OPERATION...................................................................................................................14

3.1 Page Read....................................................................................................................................14

3.2 Data Handiling Restriction During Program Sequences......................................................................14

3.3 Page Program...............................................................................................................................14

3.4 Multiple plane program..................................................................................................................15

3.5 Block Erase...................................................................................................................................15

3.6 Multiple plane Block Erase..............................................................................................................16

3.7 Copy-Back Program.......................................................................................................................16

3.8 Multiple plane copy back Program...................................................................................................17

3.9 Special read for copy back..............................................................................................................17

3.10 EDC Operation........................................................................................................................17

3.11 Read Status Register...................................................................................................................19

3.12 Read Status Enhanced.................................................................................................................19

3.13 Read Status Register field definition..............................................................................................20

3.14 Read EDC Status Register............................................................................................................20

3.15 Reset.........................................................................................................................................21

3.16 Cache Read................................................................................................................................21

3.17 Cache Program...........................................................................................................................22

3.18 Multi-plane Cache Program..........................................................................................................22

3.19 Read ID......................................................................................................................................24

3.20 Read ONFI Signature...................................................................................................................26

3.21 Read Parameter Page..................................................................................................................26

3.22 Parameter Page Data Structure Definition......................................................................................26

4 OTHER FEATURES.......................................................................................................................30

4.1 Data Protection and Power on / off sequence...................................................................................30

4.2 Ready/Busy..................................................................................................................................30

4.3 Write protect (#WP) handling........................................................................................................30

5 Device Parameters......................................................................................................................31

6 Timing Diagrams.........................................................................................................................35

7 Package Mechanical...............................................................................................................58

7.1 Power consumptions and pin capacitance for allowed stacking configurations.....................................59

8 Application notes and comments.............................................................................................60

8.1 System Interface using CE# don't care..........................................................................................60

8.2 System Bad Block Replacement....................................................................................................61

8.3 Bad Block Management System....................................................................................................62

*ba53f20d-240c*

B34416/177.179.157.84/2010-10-08 10:08

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