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RT

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UCC1895, UCC2895, UCC3895

www.ti.com

SLUS157P – DECEMBER 1999 – REVISED JUNE 2013

DELAB and DELCD source about 1 mA maximum. Choose the delay resistors so that this maximum is not

exceeded. Programmable output delay is defeated by tying DELAB and, or, DELCD to REF. For an optimum

performance keep stray capacitance on these pins at less than 10 pF.

EAOUT, EAP, and EAN (Error Amplifier)

EAOUT connects internally to the non-inverting input of the PWM comparator and the no-load comparator.

EAOUT is internally clamped to the soft-start voltage. The no-load comparator shuts down the output stages

when EAOUT falls below 500 mV, and allows the outputs to turn on again when EAOUT rises above 600 mV.

EAP is the non-inverting and the EAN is the inverting input to the error amplifier.

OUTA, OUTB, OUTC, and OUTD (Output MOSFET Drivers)

The four outputs are 100-mA complementary MOS drivers, and are optimized to drive MOSFET driver circuits.

OUTA and OUTB are fully complementary, (assuming no programming delay) and operate near 50% duty cycle

and one-half the oscillator frequency. OUTA and OUTB are intended to drive one half-bridge circuit in an external

power stage. OUTC and OUTD drive the other half-bridge and have the same characteristics as OUTA and

OUTB. OUTC is phase shifted with respect to OUTA, and OUTD is phase shifted with respect to OUTB.

NOTE

Changing the phase relationship of OUTC and OUTD with respect to OUTA and OUTB

requires other than the nominal 50% duty ratio on OUTC and OUTD during those

transients.

PGND (Power Ground)

To keep output switching noise from critical analog circuits, the UCC3895 has two different ground connections.

PGND is the ground connection for the high-current output stages. Both GND and PGND must be electrically tied

together. Also, because PGND carries high current, board traces must be low impedance.

RAMP (Inverting Input of the PWM Comparator)

(plus slope compensation) in peak current-mode control.

REF (Voltage Reference)

The 5-V ± 1.2% reference supplies power to internal circuitry, and also supplies up to 5 mA to external loads.

The reference is shutdown during undervoltage lockout but is operational during all other disable modes. For

best performance, bypass with a 0.1-

μF low-ESR low-ESL capacitor to GND. To ensure the stability of the

internal reference, do not use more than 1.0

μF of total capacitance on this pin for the UCC1895.

For the UCC2895 and the UCC3895, this capacitance increases as per the limits defined in the

RECOMMENDED OPERATING CONDITIONS table of this specification.

RT (Oscillator Timing Resistor)

(4)

Figure 3).

GND (Analog Ground)

This pin is the chip ground for all internal circuits except the output stages.

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