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UCC2972 Datasheet(PDF) 4 Page - Texas Instruments |
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UCC2972 Datasheet(HTML) 4 Page - Texas Instruments |
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4 / 24 page  4 UCC1972/3 UCC2972/3 UCC3972/3 BUCK: Senses the voltage on the top side of the induc- tor feeding the resonant tank. The voltage at this point is used to synchronize the internally generated ramp and to detect whether an open lamp condition exists. An open lamp condition exists when this voltage is be- low the specified threshold for seven clock cycles. If the MODE pin is held below the open lamp detect enable threshold, this protective feature is disabled. On the UCC3973, this pin is also used to sense an over-voltage across the transformer primary. If the volt- age at this pin exceeds the clamp threshold, current will be sourced fron the FB pin. COMP: Output of the error amplifier.Compensation components set the bandwidth of the entire system and are normally connected between COMP and FB. The error amplifier averages lamp current against a fixed in- ternal reference. The resulting voltage on the COMP pin is compared to an internally generated ramp, set- ting the PWM duty cycle. During UVLO, this pin is ac- tively pulled low. FB: This pin is the inverting input to the error amplifier. On the UCC3973, current is sourced form this pin if the clamp threshold is exceeded at the BUCK pin (see be- low). The sourced current will reduce OUT duty cycle to control transformer primary voltage. The source current is disabled on the UCC3972. GND: Ground reference for the IC. MODE: The voltage on this pin is used to control start-up and various modes of operation for the part (refer to the ta- ble in the block diagram). When the voltage is below 1V, OUT is forced low, open lamp detection is disabled and the error amplifier is tri-stated. When the voltage is between 1V and 3V, OUT is enabled and the error amplifier output is connected to COMP. Open lamp detection is still disabled and a constant 20 A current is sourced from this pin. Placing an appropriate value ex- ternal capacitor between this pin and ground allows the user to disable open lamp detection for a set period of time at start-up to allow the lamp to strike. When MODE reaches 3V, open lamp detection is enabled and normal operation is activated. OUT: Drives the buck regulator N-channel MOSFET. OUT turn-on is synchronized to twice the tank resonant fre- quency. OUT is actively pulled low when in UVLO, an open lamp condition has been detected or MODE is less than 1V. VBAT: Positive input supply to power stage. This voltage is required by internal control circuitry to provide open-lamp detection and synchronization. Operating range is from 4.5V to 25V. VDD: This pin connects to the battery voltage from which the CCFL inverter will operate. If the potential on VBAT can exceed 18V in the application, a series resistor must be placed between VBAT and this pin (see applications section). The voltage at the VDD pin will then be regulated to 18V. This pin should be bypassed with a minimum ca- pacitance of 0.1 mF. PIN DESCRIPTIONS 0 200 400 600 800 8.7 9.2 9.7 VBAT -VBUCK Clamp current vs. tank voltage for UCC3973. |
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