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ADG426BN Datasheet(PDF) 11 Page - Analog Devices |
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ADG426BN Datasheet(HTML) 11 Page - Analog Devices |
11 / 20 page ADG406/ADG407/ADG426 Rev. B | Page 11 of 20 VDD 1 NC 2 3 S16 4 D 28 VSS 27 S8 26 S7 25 S15 5 S14 6 S13 7 S6 24 S5 23 S4 22 S12 8 S3 21 S11 9 S2 20 S10 10 S1 19 S9 11 EN 18 GND 12 A0 17 A1 16 13 A3 14 A2 15 NC = NO CONNECT ADG426 TOP VIEW (Not to Scale) WR RS Figure 10. 28-Lead PDIP/SSOP Table 8. Pin Function Descriptions Pin No. Mnemonic Description 1 VDD Most Positive Power Supply Potential. 2 NC No Connect. 3 RS Active Low Logic Input. When this pin is low, all switches are open, and address and enable latches registers are cleared to 0. 4 to 11 S16 to S9 Source Terminal 16 to Source Terminal 9. These pins can be inputs or outputs. 12 GND Ground (0 V) Reference. 13 WR The rising edge of the WR signal latches the state of the address control lines and the enable line. 14 to 17 A3 to A0 Logic Control Input. 18 EN Active High Digital Input. When this pin is low, the device is disabled and all switches are turned off. When this pin is high, the Ax logic inputs determine which switch is turned on. 19 to 26 S1 to S8 Source Terminal 1 to Source Terminal 8. These pins can be inputs or outputs. 27 VSS Most Negative Power Supply Potential. In single-supply applications, this pin can be connected to ground. 28 D Drain Terminal. This pin can be an input or an output. Table 9. Truth Table (ADG426) A3 A2 A1 A0 EN WR RS On switch X X X X X 1 Retains previous switch condition X X X X X X 0 None (address and enable latches cleared) X X X X 0 0 1 None 0 0 0 0 1 0 1 1 0 0 0 1 1 0 1 2 0 0 1 0 1 0 1 3 0 0 1 1 1 0 1 4 0 1 0 0 1 0 1 5 0 1 0 1 1 0 1 6 0 1 1 0 1 0 1 7 0 1 1 1 1 0 1 8 1 0 0 0 1 0 1 9 1 0 0 1 1 0 1 10 1 0 1 0 1 0 1 11 1 0 1 1 1 0 1 12 1 1 0 0 1 0 1 13 1 1 0 1 1 0 1 14 1 1 1 0 1 0 1 15 1 1 1 1 1 0 1 16 |
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