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AD5302BRMZ-REEL7 Datasheet(PDF) 8 Page - Analog Devices |
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AD5302BRMZ-REEL7 Datasheet(HTML) 8 Page - Analog Devices |
8 / 24 page AD5302/AD5312/AD5322 Rev. D | Page 8 of 24 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS LDAC 1 VDD 2 VREFB 3 VREFA 4 VOUTA 5 GND 10 DIN 9 SCLK 8 SYNC 7 VOUTB 6 AD5302/ AD5312/ AD5322 TOP VIEW (Not to Scale) Figure 5. Pin Configuration Table 5. Pin Function Descriptions Pin No. Mnemonic Description 1 LDAC Active Low Control Input. This pin transfers the contents of the input registers to their respective DAC registers. Pulsing LDAC low allows either or both DAC registers to be updated if the input registers have new data. This allows simultaneous updating of both DAC outputs. 2 VDD Power Supply Input. The parts can be operated from 2.5 V to 5.5 V, and the supply should be decoupled to GND. 3 VREFB Reference Input Pin for DAC B. This is the reference for DAC B. It can be configured as a buffered or an unbuffered input, depending on the BUF bit in the control word of DAC B. It has an input range of 0 V to VDD in unbuffered mode and 1 V to VDD in buffered mode. 4 VREFA Reference Input Pin for DAC A. This is the reference for DAC A. It can be configured as a buffered or an unbuffered input depending on the BUF bit in the control word of DAC A. It has an input range of 0 V to VDD in unbuffered mode and 1 V to VDD in buffered mode. 5 VOUTA Buffered Analog Output Voltage from DAC A. The output amplifier has rail-to-rail operation. 6 VOUTB Buffered Analog Output Voltage from DAC B. The output amplifier has rail-to-rail operation. 7 SYNC Active Low Control Input. This is the frame synchronization signal for the input data. When SYNC goes low, it powers on the SCLK and DIN buffers and enables the input shift register. Data is transferred in on the falling edges of the following 16 clocks. If SYNC is taken high before the 16th falling edge, the rising edge of SYNC acts as an interrupt and the write sequence is ignored by the device. 8 SCLK Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock input. Data can be transferred at rates up to 30 MHz. The SCLK input buffer is powered down after each write cycle. 9 DIN Serial Data Input. This device has a 16-bit input shift register. Data is clocked into the register on the falling edge of the serial clock input. The DIN input buffer is powered down after each write cycle. 10 GND Ground Reference Point for All Circuitry on the Part. |
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