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SST25WF020A-40-5I-SN Datasheet(PDF) 6 Page - Microchip Technology |
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SST25WF020A-40-5I-SN Datasheet(HTML) 6 Page - Microchip Technology |
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6 / 36 page  SST25WF020A DS21392A-page 6 Preliminary 2013 Microchip Technology Inc. 4.2 Status Register The software status register provides status on whether the flash memory array is available for any Read or Write operation, whether the device is Write enabled, and the state of the Memory Write protection. During an internal Erase or Program operation, the sta- tus register may be read only to determine the comple- tion of an operation in progress. Table 4-2 describes the function of each bit in the software status register. 4.2.1 BUSY (BIT 0) The Busy bit determines whether there is an internal Erase or Program operation in progress. A ‘1’ for the Busy bit indicates the device is busy with an operation in progress. A ‘0’ indicates the device is ready for the next valid operation. 4.2.2 WRITE ENABLE LATCH (WEL–BIT 1) The Write-Enable-Latch bit indicates the status of the internal Write-Enable-Latch memory. If the WEL bit is set to ‘1’, it indicates the device is Write enabled. If the bit is set to ‘0’ (reset), it indicates the device is not Write enabled and does not accept any Write (Program/ Erase) commands. The Write-Enable-Latch bit is auto- matically reset under the following conditions: • Power-up • Write-Disable (WRDI) instruction completion • Page-Program instruction completion • Sector-Erase instruction completion • 64 KByte Block-Erase instruction completion • Chip-Erase instruction completion • Write-Status-Register instruction completion 4.2.3 BLOCK-PROTECTION (BP0, BP1, AND TB–BITS 2, 3, AND 5) The Block-Protection (BP0, BP1, and TB) bits define the size of the memory area to be software protected against any memory Write (Program or Erase) opera- tion, see Table 4-3. The Write-Status-Register (WRSR) instruction is used to program the BP0, BP1, and TB bits as long as WP# is high or the Block-Protect-Lock (BPL) bit is ‘0’. Chip-Erase can only be executed if Block-Protection bits are all ‘0’. BP0 and BP1 select the protected area and TB allocates the protected area to the higher-order address area (Top Blocks) or lower- order address area (Bottom Blocks). TABLE 4-2: SOFTWARE STATUS REGISTER Bit Name Function Default at Power-up Read/Write 0 BUSY 1 = Internal Write operation is in progress 0 = No internal Write operation is in progress 0R 1 WEL 1 = Device is memory Write enabled 0 = Device is not memory Write enabled 0R 2 BP01 1. BP0, BP1, TB, and BPL bits are non-volatile memory bits. Indicate current level of block write protection (See Table 4-3) 0 or 1 R/W 3 BP11 Indicate current level of block write protection (See Table 4-3) 0 or 1 R/W 4 RES Reserved for future use 0 N/A 5TB1 1 = 1/4 or 1/2 Bottom Memory Blocks are protected (See Table 4-3) 0 = 1/2 or 1/4 Top Memory Blocks are protected 0 or 1 R/W 6 RES Reserved for future use 0 N/A 7 BPL1 1 = BP0, BP1, TB, and BPL are read-only bits 0 = BP0, BP1, TB, and BPL are read/writable 0 or 1 R/W |
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