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CY2305 Datasheet(PDF) 6 Page - Cypress Semiconductor

Part # CY2305
Description  3.3 V Zero Delay Clock Buffer
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Manufacturer  CYPRESS [Cypress Semiconductor]
Direct Link  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

CY2305 Datasheet(HTML) 6 Page - Cypress Semiconductor

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CY2305C
CY2309C
Document Number: 38-07672 Rev. *L
Page 6 of 21
Figure 3. REF. Input to CLKA/CLKB Delay vs. Loading Difference between CLKOUT and CLKA/CLKB pins
Zero Delay and Skew Control
All outputs must be uniformly loaded to achieve Zero Delay
between the input and output. Since the CLKOUT pin is the
internal feedback to the PLL, its relative loading can adjust the
input or output delay.
For applications requiring zero input or output delay, all outputs
including CLKOUT are equally loaded. Even if CLKOUT is not
used, it must have a capacitive load equal to that on other
outputs for obtaining zero input or output delay.
For zero output to output skew, all outputs must be loaded
equally.
Even if CLKOUT is not used, it must have a capacitive load,
equal to that on other outputs, for obtaining zero input-output
delay. If input to output delay adjustments are required, use
Figure 3 to calculate loading differences between the CLKOUT
pin and other outputs.
Select Input Decoding
For CY2309C
S2
S1
CLOCK A1–A4
CLOCK B1–B4
CLKOUT [4]
Output Source
PLL Shutdown
0
0
Three state
Three state
Driven
PLL
N
0
1
Driven
Three state
Driven
PLL
N
1
0
Driven
Driven
Driven
Reference
Y
1
1
Driven
Driven
Driven
PLL
N
Note
4. This output is driven and has an internal feedback for the PLL. The load on this output is adjusted to change the skew between the reference and output.


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