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LCMXO2-1200ZE-2MG132C Datasheet(PDF) 7 Page - Lattice Semiconductor

Part # LCMXO2-1200ZE-2MG132C
Description  MachXO2??Family Data Sheet
Download  106 Pages
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Manufacturer  LATTICE [Lattice Semiconductor]
Direct Link  http://www.latticesemi.com
Logo LATTICE - Lattice Semiconductor

LCMXO2-1200ZE-2MG132C Datasheet(HTML) 7 Page - Lattice Semiconductor

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2-3
Architecture
MachXO2 Family Data Sheet
Slices
Slices 0-3 contain two LUT4s feeding two registers. Slices 0-2 can be configured as distributed memory. Table 2-1
shows the capability of the slices in PFU blocks along with the operation modes they enable. In addition, each PFU
contains logic that allows the LUTs to be combined to perform functions such as LUT5, LUT6, LUT7 and LUT8.
The control logic performs set/reset functions (programmable as synchronous/ asynchronous), clock select, chip-
select and wider RAM/ROM functions.
Table 2-1. Resources and Modes Available per Slice
Figure 2-4 shows an overview of the internal logic of the slice. The registers in the slice can be configured for posi-
tive/negative and edge triggered or level sensitive clocks. All slices have 15 inputs from routing and one from the
carry-chain (from the adjacent slice or PFU). There are seven outputs: six for routing and one to carry-chain (to the
adjacent PFU). Table 2-2 lists the signals associated with Slices 0-3.
Figure 2-4. Slice Diagram
Slice
PFU Block
Resources
Modes
Slice 0
2 LUT4s and 2 Registers
Logic, Ripple, RAM, ROM
Slice 1
2 LUT4s and 2 Registers
Logic, Ripple, RAM, ROM
Slice 2
2 LUT4s and 2 Registers
Logic, Ripple, RAM, ROM
Slice 3
2 LUT4s and 2 Registers
Logic, Ripple, ROM
LUT4 &
Carry
Slice
Flip-flop/
Latch
OFX0
F0
Q0
CI
CO
LUT4 &
Carry
CI
CO
OFX1
F1
Q1
F/SUM
F/SUM
D
D
FCI From
Different
Slice/PFU
Memory &
Control
Signals
FCO To Different Slice/PFU
LUT5
Mux
From
Routing
To
Routing
For Slices 0 and 1, memory control signals are generated from Slice 2 as follows:
• WCK is CLK
• WRE is from LSR
• DI[3:2] for Slice 1 and DI[1:0] for Slice 0 data from Slice 2
• WAD [A:D] is a 4-bit address from slice 2 LUT input
A0
C0
D0
A1
B1
C1
D1
CE
CLK
LSR
M1
M0
FXB
FXA
B0
Flip-flop/
Latch


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