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PIC18F46K22 Datasheet(PDF) 10 Page - Microchip Technology |
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PIC18F46K22 Datasheet(HTML) 10 Page - Microchip Technology |
10 / 42 page PIC18(L)F2XK22/4XK22 DS41398B-page 10 Advance Information 2010 Microchip Technology Inc. 2.4 High-Level Overview of the Programming Process Figure 2-11 shows the high-level overview of the programming process. First, a Bulk Erase is performed. Next, the code memory, ID locations and data EEPROM are programmed. These memories are then verified to ensure that programming was successful. If no errors are detected, the Configuration bits are then programmed and verified. FIGURE 2-11: HIGH-LEVEL PROGRAMMING FLOW 2.5 Entering and Exiting High-Voltage ICSP Program/Verify Mode As shown in Figure 2-12, the High-Voltage ICSP Program/Verify mode is entered by holding PGC and PGD low and then raising MCLR/VPP/RE3 to VIHH (high voltage). Once in this mode, the code memory, data EEPROM, ID locations and Configuration bits can be accessed and programmed in serial fashion. Figure 2-13 shows the exit sequence. The sequence that enters the device into the Program/ Verify mode places all unused I/Os in the high-impedance state. FIGURE 2-12: ENTERING HIGH-VOLTAGE PROGRAM/VERIFY MODE FIGURE 2-13: EXITING HIGH-VOLTAGE PROGRAM/VERIFY MODE Start Program Memory Program IDs Program Data EE Verify Program Verify IDs Verify Data Program Configuration Bits Verify Configuration Bits Done Perform Bulk Erase MCLR/VPP/RE3 P12 PGD PGD = Input PGC VDD D110 P13 P1 MCLR/VPP/RE3 P16 PGD PGD = Input PGC VDD D110 P17 P1 |
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