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TAS2505 Datasheet(PDF) 11 Page - Texas Instruments |
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TAS2505 Datasheet(HTML) 11 Page - Texas Instruments |
11 / 34 page T0146-09 WCLK BCLK DIN t (WS) d t (WS) d t (DI) S t (DI) h t f t r TAS2505 www.ti.com SLAS778A – FEBRUARY 2013 – REVISED FEBRUARY 2013 3.5.3 DSP Timing in Master Mode All specifications at 25°C, DVDD = 1.8 V Note: All timing specifications are measured at characterization but not tested at final test. IOVDD = 1.8 V IOVDD = 3.3 V PARAMETER UNIT MIN MAX MIN MAX td(WS) WCLK delay 45 45 ns ts(DI) DIN setup 8 6 ns th(DI) DIN hold 8 6 ns tr Rise time 25 10 ns tf Fall time 25 10 ns Figure 3-3. DSP Timing in Master Mode Copyright © 2013, Texas Instruments Incorporated ELECTRICAL SPECIFICATIONS 11 Submit Documentation Feedback Product Folder Links: TAS2505 |
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