256MB, 512MB (x64, DR)

144-PIN SDRAM SODIMM

pdf: 09005aef807924d2, source: 09005aef807924f1

Micron Technology, Inc., reserves the right to change products or specifications without notice.

SDF16C32_64x64HG.fm - Rev. E 4/06 EN

9

©2006 Micron Technology, Inc. All rights reserved.

NOTE:

1. For full-page accesses: y = 1,024 (both 256MB and

512MB modules)

2. For a burst length of two, A1–A9 select the block-of-

two burst; A0 selects the starting column within the

block.

3. For a burst length of four, A2–A9 select the block-of-

four burst; A0–A1 select the starting column within the

block.

4. For a burst length of eight, A3–A9 select the block-of-

eight burst; A0–A2 select the starting column within

the block.

5. For a full-page burst, the full row is selected and A0–A9

select the starting column.

6. Whenever a boundary of the block is reached within a

given sequence above, the following access wraps

within the block.

7. For a burst length of one, A0–A9 select the unique col-

umn to be accessed, and mode register bit M3 is

ignored.

Figure 5: CL Diagram

Burst Type

Accesses within a given burst may be programmed

to be either sequential or interleaved; this is referred to

as the burst type and is selected via bit M3.

The ordering of accesses within a burst is deter-

mined by the burst length, the burst type, and the

starting column address, as shown in Table 7.

CAS Latency (CL)

CL is the delay, in clock cycles, between the registra-

tion of a READ command and the availability of the

first piece of output data. The latency can be set to two

or three clocks.

If a READ command is registered at clock edge n,

and the latency is m clocks, the data will be available

by clock edge n + m. The DQ will start driving as a

result of the clock edge one cycle earlier (n + m - 1),

and provided that the relevant access times are met,

the data will be valid by clock edge n + m. For example,

assuming that the clock cycle time is such that all rele-

vant access times are met, if a READ command is regis-

tered at T0 and the latency is programmed to two

clocks, the DQ will start driving after T1 and the data

will be valid by T2, as shown in Figure 4 on page 8.

Table 8 on page 10 indicates the operating frequencies

at which each CL setting can be used.

Reserved states should not be used as unknown

operation or incompatibility with future versions may

result.

Table 7:

Burst Definition Table

BURST

LENGTH

STARTING

COLUMN

ADDRESS

ORDER OF ACCESSES

WITHIN A BURST

TYPE =

SEQUENTIAL

TYPE =

INTERLEAVED

2

A0

00-1

0-1

11-0

1-0

4

A1 A0

0

0

0-1-2-3

0-1-2-3

0

1

1-2-3-0

1-0-3-2

1

0

2-3-0-1

2-3-0-1

1

1

3-0-1-2

3-2-1-0

8

A2 A1 A0

0

0

0

0-1-2-3-4-5-6-7

0-1-2-3-4-5-6-7

0

0

1

1-2-3-4-5-6-7-0

1-0-3-2-5-4-7-6

0

1

0

2-3-4-5-6-7-0-1

2-3-0-1-6-7-4-5

0

1

1

3-4-5-6-7-0-1-2

3-2-1-0-7-6-5-4

1

0

0

4-5-6-7-0-1-2-3

4-5-6-7-0-1-2-3

1

0

1

5-6-7-0-1-2-3-4

5-4-7-6-1-0-3-2

1

1

0

6-7-0-1-2-3-4-5

6-7-4-5-2-3-0-1

1

1

1

7-0-1-2-3-4-5-6

7-6-5-4-3-2-1-0

Full

Page

(y)

n = A0-A9

(location

0-y)

Cn, Cn + 1, Cn + 2

Cn + 3, Cn + 4...

…Cn - 1, Cn…

Not supported

CLK

DQ

T2

T1

T3

T0

CAS Latency = 3

LZ

tOH

t

COMMAND

NOP

READ

tAC

NOP

T4

NOP

DON’T CARE

UNDEFINED

CLK

DQ

T2

T1

T3

T0

CAS Latency = 2

LZ

tOH

t

COMMAND

NOP

READ

tAC

NOP