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MT16LSDF6464LHY-133 Datasheet(PDF) 8 Page - Micron Technology |
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MT16LSDF6464LHY-133 Datasheet(HTML) 8 Page - Micron Technology |
8 / 22 page 256MB, 512MB (x64, DR) 144-PIN SDRAM SODIMM pdf: 09005aef807924d2, source: 09005aef807924f1 Micron Technology, Inc., reserves the right to change products or specifications without notice. SDF16C32_64x64HG.fm - Rev. E 4/06 EN 8 ©2006 Micron Technology, Inc. All rights reserved. Mode register bits M0–M2 specify the burst length, M3 specifies the type of burst (sequential or inter- leaved), M4–M6 specify the CL, M7 and M8 specify the operating mode, M9 specifies the write burst mode, and M10 and M11 are reserved for future use. For the 256MB and 512MB, M12 (A12) is undefined, but should be driven LOW during loading of the mode reg- ister. The mode register must be loaded when all device banks are idle, and the controller must wait the speci- fied time before initiating the subsequent operation. Violating either of these requirements will result in unspecified operation. Burst Length Read and write accesses to the SDRAM are burst ori- ented, with the burst length being programmable, as shown in Figure 4. The burst length determines the maximum number of column locations that can be accessed for a given READ or WRITE command. Burst lengths of 1, 2, 4, or 8 locations are available for both the sequential and the interleaved burst types, and a full-page burst is available for the sequential type. The full-page burst is used in conjunction with the BURST TERMINATE command to generate arbitrary burst lengths. Reserved states should not be used, as unknown operation or incompatibility with future versions may result. When a READ or WRITE command is issued, a block of columns equal to the burst length is effectively selected. All accesses for that burst take place within this block, meaning that the burst will wrap within the block if a boundary is reached, as shown in Table 7 on page 9. The block is uniquely selected by A1–A9 when the burst length is set to two; by A2–A9 when the burst length is set to four; and by A3–A9 when the burst length is set to eight. The remaining (least significant) address bit(s) is (are) used to select the starting loca- tion within the block. Full-page bursts wrap within the page if the boundary is reached, as shown in Table 7 on page 9. Figure 4: Mode Register Definition Diagram M3 = 0 1 2 4 8 Reserved Reserved Reserved Full Page M3 = 1 1 2 4 8 Reserved Reserved Reserved Reserved Operating Mode Standard operation All other states reserved 0 - 0 - Defined - 0 1 Burst Type Sequential Interleaved CAS Latency Reserved Reserved 2 3 Reserved Reserved Reserved Reserved Burst Length 512MB Module 256MB Module M0 0 1 0 1 0 1 0 1 Burst Length CAS LatencyBT A9 A7 A6 A5 A4 A3 A8 A2 A1 A0 Mode Register (Mx) Address Bus 97 6 54 3 82 1 0 M1 0 0 1 1 0 0 1 1 M2 0 0 0 0 1 1 1 1 M3 M4 0 1 0 1 0 1 0 1 M5 0 0 1 1 0 0 1 1 M6 0 0 0 0 1 1 1 1 M6-M0 M8 M7 Op Mode A10 A11 10 11 Reserved*WB 0 1 Write Burst Mode Programmed burst length Single location access M9 *Should program M12, M11, and M10 = “0, 0, 0” to ensure compatibility with future devices. *Should program M11 and M10 = “0, 0” to ensure compatibility with future devices. A12 12 Burst Length CAS LatencyBT A9 A7 A6 A5 A4 A3 A8 A2 A1 A0 Mode Register (Mx) Address Bus 97 6 54 3 82 1 0 Op Mode A10 A11 10 11 Reserved* WB |
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