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M393B1G70BH0 Datasheet(PDF) 5 Page - Samsung semiconductor |
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M393B1G70BH0 Datasheet(HTML) 5 Page - Samsung semiconductor |
5 / 55 page - 5 - datasheet DDR3 SDRAM Rev. 1.5 Registered DIMM 1. DDR3 Registered DIMM Ordering Information NOTE : 1. "##" - F8/H9/K0/MA 2. F8(1066Mbps 7-7-7) / H9(1333Mbps 9-9-9) / K0(1600Mbps 11-11-11) / MA(1866Mbps 13-13-13) - DDR3-1866(13-13-13) is backward compatible to DDR3-1600(11-11-11), DDR3-1333(9-9-9), DDR3-1066(7-7-7) - DDR3-1600(11-11-11) is backward compatible to DDR3-1333(9-9-9), DDR3-1066(7-7-7) - DDR3-1333(9-9-9) is backward compatible to DDR3-1066(7-7-7) 2. Key Features • JEDEC standard 1.5V ± 0.075V Power Supply •VDDQ = 1.5V ± 0.075V • 400MHz fCK for 800Mb/sec/pin, 533MHz fCK for 1066Mb/sec/pin, 667MHz fCK for 1333Mb/sec/pin, 800MHz fCK for 1600Mb/sec/pin, 933MHz fCK for 1866Mb/sec/pin • 8 independent internal bank • Programmable CAS Latency: 6,7,8,9,10,11,13 • Programmable Additive Latency(Posted CAS) : 0, CL - 2, or CL - 1 clock • Programmable CAS Write Latency(CWL) = 5(DDR3-800), 6(DDR3-1066), 7(DDR3-1333), 8(DDR3-1600) and 9(DDR3-1866) • Burst Length: 8 (Interleave without any limit, sequential with starting address “000” only), 4 with tCCD = 4 which does not allow seamless read or write [either On the fly using A12 or MRS] • Bi-directional Differential Data Strobe • On Die Termination using ODT pin • Average Refresh Period 7.8us at lower then TCASE 85C, 3.9us at 85C < TCASE 95C • Asynchronous Reset 3. Address Configuration Part Number2 Density Organization Component Composition1 Number of Rank Height M393B1G70BH0-CF8/H9/K0/MA 8GB 1Gx72 1Gx4(K4B4G0446B-HC##)*18 1 30mm M393B1G73BH0-CF8/H9/K0/MA 8GB 1Gx72 512Mx8(K4B4G0846B-HC##)*18 2 30mm M393B2G70BH0-CF8/H9/K0/MA 16GB 2Gx72 1Gx4(K4B4G0446B-HC##)*36 2 30mm M393B2G73BH0-CF8/H9 16GB 2Gx72 512Mx8(K4B4G0846B-HC##)*36 4 30mm M393B4G70BM0-CF8/H9 32GB 4Gx72 DDP 2Gx4(K4B8G0446B-MC##)*36 4 30mm Speed DDR3-800 DDR3-1066 DDR3-1333 DDR3-1600 DDR3-1866 Unit 6-6-6 7-7-7 9-9-9 11-11-11 13-13-13 tCK(min) 2.5 1.875 1.5 1.25 1.071 ns CAS Latency 6 7 9 11 13 nCK tRCD(min) 15 13.125 13.5 13.75 13.91 ns tRP(min) 15 13.125 13.5 13.75 13.91 ns tRAS(min) 37.5 37.5 36 35 34 ns tRC(min) 52.5 50.625 49.5 48.75 47.91 ns Organization Row Address Column Address Bank Address Auto Precharge 1Gx4(4Gb) based Module A0-A15 A0-A9, A11 BA0-BA2 A10/AP 512Mx8(4Gb) based Module A0-A15 A0-A9 BA0-BA2 A10/AP 2Gx4(8Gb DDP) based Module A0-A15 A0-A9, A11 BA0-BA2 A10/AP |
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