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AFE7071 Datasheet(PDF) 5 Page - Texas Instruments |
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AFE7071 Datasheet(HTML) 5 Page - Texas Instruments |
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5 / 36 page  AFE7071 www.ti.com SLOS789C – MAY 2012 – REVISED JANUARY 2012 ELECTRICAL CHARACTERISTICS Typical values at TA = 25°C, full temperature range is TMIN = –40°C to TMAX = 85°C, DAC sampling rate = 65 MSPS, DVDD18 = 1.8 V, CLKVDD18 = 1.8 V, DACVDD18 = 1.8 V, FUSEVDD18 = 1.8 V, IOVDD = 3.3 V, DACVDD33 = 3.3 V, MODVDD33 = 3.3 V, analog output (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT DIGITAL INPUTS (D[13:0], IQ_FLAG, SDI, SCLK, SDENB, RESETB, SYNC_SLEEP, ALARM_SDO, CLK_IO) IOVDD = 3.3 V 2.3 VIH High-level input voltage IOVDD = 2.5 V 1.75 V IOVDD = 1.8 V 1.25 IOVDD = 3.3 V 1 VIL Low-level input voltage IOVDD = 2.5 V 0.75 V IOVDD = 1.8 V 0.54 IIH High-level input current IOVDD = 3.3 V –80 80 µA IIL Low-level input current IOVDD = 3.3 V –80 80 µA Ci Input capacitance 5 pF fDAC DAC sample rate Interleaved data, fDAC = 1/2 × fINPUT 0 65 MSPS fINPUT Input data rate Interleaved data, fINPUT = 2 × fDAC 0 130 MSPS DIGITAL OUTPUTS (ALARM_SDO, SDIO, CLK_IO) ILOAD = –100 µA IOVDD – 0.2 V VOH High-level output voltage ILOAD = –2 mA 0.8 × IOVDD V ILOAD = 100 µA 0.2 V VOL Low-level output voltage ILOAD = 2 mA 0.22 × IOVDD V CLOCK INPUT (DACCLKP/DACCLKN) DACCLKP/N duty cycle 40% 60% DACCLKP/N differential voltage 0.4 1 V Timing Parallel Data Input (D[13:0], IQ_FLAG, SYNC_SLEEP) – Dual Input Clock Mode tSU Input setup time Relative to CLK_IO rising edge 1 0.2 ns tH Input hold time Relative to CLK_IO rising edge 1 0.2 ns tLPH Input clock pulse high time 3 ns Timing Parallel Data Input (D[13:0], IQ_FLAG, SYNC_SLEEP) – Dual Output Clock Mode tSU Input setup time Relative to CLK_IO rising edge 1 0.2 ns tH Input hold time Relative to CLK_IO rising edge 1 0.2 ns Timing Parallel Data Input (D[13:0], IQ_FLAG, SYNC_SLEEP) – Single Differential DDR and SDR Clock Modes tSU Input setup time Relative to DACCLKP/N rising edge 0 –0.8 ns tH Input hold time Relative to DACCLKP/N rising edge 2 1.2 ns Timing – Serial Data Interface tS(SDENB) Setup time, SDENB to rising edge of SCLK 20 ns tS(SDIO) Setup time, SDIO valid to rising edge of SCLK 10 ns tH(SDIO) Hold time, SDIO valid to rising edge of SCLK 5 ns tSCLK Period of SCLK 100 ns tSCLKH High time of SCLK 40 ns tSCLKL Low time of SCLK 40 ns tD(DATA) Data output delay after falling edge of SCLK 10 ns tRESET Minimum RESETB pulse duration 25 ns Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback 5 Product Folder Links: AFE7071 |
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