UCC2891, UCC2892

UCC2893, UCC2894

SLUS542F − OCTOBER 2003 − REVISED JULY 2009

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DETAILED PIN DESCRIPTIONS

RDEL (pin 1)

turn-on delay for both gate drive signals of the UCC2981 family of controllers. The delay time is identical for both

switching transitions, between OUT (pin 13) is turning off and AUX (pin 14) is turning on as well as when AUX

(pin 14) is turning off and OUT (pin 13) is turning on. The delay time is defined as:

t

R

For proper selection of the delay time refer to the various references describing the design of active clamp power

converters.

RTON (pin 2)

charge current of the internal timing capacitor. The RTON pin, in conjunction with the RTOFF pin (pin 3) are used

to set the operating frequency and maximum operating duty cycle of the UCC2891 family.

RTOFF (pin3)

discharge current of the internal timing capacitor. The RTON and RTOFF pins are used to set the switching

t

R

t

R

T

D

t

ON

T

SW

VREF (pin 4)

The controller’s internal, 5-V bias rail is connected to this pin. The internal bias regulator requires a good quality

by stability considerations of the bias regulator, while the maximum is approximately 22-

µF. Also, capacitor

value on VDD should be minimum 10 times greater than that on VREF.

The VREF pin is internally current limited and can supply approximately 5-mA to external circuits. The 5-V bias

is only available when the undervoltage lock out (UVLO) circuit enables the operation of UCC289x controllers.

For the detailed functional description of the undervoltage lock out (UVLO) circuit refer to the Functional

Description section of this datasheet.

(1)

(2)

(3)

(4)

(5)