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FDMC86102LZ Datasheet(PDF) 2 Page - Fairchild Semiconductor |
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FDMC86102LZ Datasheet(HTML) 2 Page - Fairchild Semiconductor |
2 / 7 page ©2011 Fairchild Semiconductor Corporation 2 www.fairchildsemi.com FDMC86102LZ Rev. C Electrical Characteristics T J = 25 °C unless otherwise noted Off Characteristics On Characteristics Dynamic Characteristics Switching Characteristics Drain-Source Diode Characteristics Symbol Parameter Test Conditions Min Typ Max Units BVDSS Drain to Source Breakdown Voltage ID = 250 μA, VGS = 0 V 100 V ΔBV DSS ΔT J Breakdown Voltage Temperature Coefficient ID = 250 μA, referenced to 25 °C 71 mV/°C IDSS Zero Gate Voltage Drain Current VDS = 80 V, VGS = 0 V 1 μA IGSS Gate to Source Leakage Current VGS = ±20 V, VDS = 0 V ±10 μA VGS(th) Gate to Source Threshold Voltage VGS = VDS, ID = 250 μA 1.0 1.6 2.2 V ΔV GS(th) ΔT J Gate to Source Threshold Voltage Temperature Coefficient ID = 250 μA, referenced to 25 °C -6 mV/°C rDS(on) Static Drain to Source On Resistance VGS = 10 V, ID = 6.5 A 19 24 m Ω VGS = 4.5 V, ID = 5.5 A 25 35 VGS = 10 V, ID = 6.5 A, TJ = 125 °C 31 40 gFS Forward Transconductance VDS = 5 V, ID = 6.5 A 24 S Ciss Input Capacitance VDS = 50 V, VGS = 0 V, f = 1 MHz 969 1290 pF Coss Output Capacitance 181 240 pF Crss Reverse Transfer Capacitance 9 15 pF Rg Gate Resistance 0.4 Ω td(on) Turn-On Delay Time VDD = 50 V, ID = 6.5 A, VGS = 10 V, RGEN = 6 Ω 7.1 15 ns tr Rise Time 2.3 10 ns td(off) Turn-Off Delay Time 19 35 ns tf Fall Time 2.5 10 ns Qg(TOT) Total Gate Charge VGS = 0 V to 10 V VDD = 50 V, ID = 6.5 A 15.3 22 nC Qg(TOT) Total Gate Charge VGS = 0 V to 4.5 V 7.6 11 nC Qgs Total Gate Charge 2.4 nC Qgd Gate to Drain “Miller” Charge 2.5 nC VSD Source to Drain Diode Forward Voltage VGS = 0 V, IS = 6.5 A (Note 2) 0.80 1.3 V VGS = 0 V, IS = 2 A (Note 2) 0.72 1.2 trr Reverse Recovery Time IF = 6.5 A, di/dt = 100 A/μs 42 67 ns Qrr Reverse Recovery Charge 40 64 nC NOTES: 1. RθJA is determined with the device mounted on a 1 in 2 pad 2 oz copper pad on a 1.5 x 1.5 in. board of FR-4 material. RθJC is guaranteed by design while RθCA is determined by the user's board design. 2. Pulse Test: Pulse Width < 300 μs, Duty cycle < 2.0%. 3. Starting TJ = 25 °C; N-ch: L = 1 mH, IAS = 13 A, VDD = 90 V, VGS = 10 V. 4. The diode connected between gate and source serves only as protection against ESD. No gate overvoltage rating is implied. 53 °C/W when mounted on a 1 in2 pad of 2 oz copper a. 125 °C/W when mounted on a minimum pad of 2 oz copper b. |
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