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TMS320DM8148BCYE2 Datasheet(PDF) 9 Page - Texas Instruments |
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TMS320DM8148BCYE2 Datasheet(HTML) 9 Page - Texas Instruments |
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9 / 370 page  TMS320DM8148, TMS320DM8147, TMS320DM8146 www.ti.com SPRS647D – MARCH 2011 – REVISED SEPTEMBER 2012 SEE ADDITIONS/MODIFICATIONS/DELETIONS Section 7.5.1, ARM Cortex-A8 Interrupts: Section 7.5 • Added a note that the AINTC for General-Purpose devices does not support the generation of FIQs Interrupts to the ARM. [Cleared E2E Issue] Table 8-3, EDMA Channel Synchronization Events: Section 8.4.1 EDMA Channel • Deleted EVENT NUMBER 54 PCIE_TX, PCIE Transmit Synchronization Events • Deleted EVENT NUMBER 55 PCIE_RX, PCIE Receive Table 8-22, Timing Requirements for EMAC RGMII Input Receive for 10/100/1000 Mbps: Section 8.6.2.3 • Deleted the "Internal delay disabled" rows from PARAMETER NO. 5, tsu(RGTXD-RGTXCH) and NO. 6, EMAC RGMII Electrical th(RGTXCH-RGTXD) Data/Timing • Deleted the "Internal delay enabled" mode option from PARAMETER NO. 5, tsu(RGTXD-RGTXCH) and NO. 6, th(RGTXCH-RGTXD) Table 8-24, Switching Characteristics Over Recommended Operating Conditions for EMAC RGMII Transmit: • Deleted the "Internal delay disabled" rows from PARAMETER NO. 5, tsu(RGTXD-RGTXCH) and NO. 6, th(RGTXCH-RGTXD) • Added PARAMETER NO. 7, tsk(RGTXD-RGTXCH), Transmit selected signals to EMAC[x]_RGTXC (at DSP) output skew, Internal delay disabled row Figure 8-16, EMAC Receive Interface Timing [RGMII Operation] : • Updated/Changed the "EMAC[x]_RGRXC must be ..." footnote register reference from "RGMII_ID_MODE_N" to "RGMIIx_ID_MODE" [Cleared E2E Issue] Figure 8-17, EMAC Transmit Interface Timing [RGMII Operation]: • Updated/Changed the figure • Updated/Changed the "RGTXC is delayed internally ..." footnote register reference from "RGMII_ID_MODE_N" to "RGMIIx_ID_MODE" [Cleared E2E Issue] Table 8-33, Switching Characteristics Over Recommended Operating Conditions for GPMC/NOR Flash Interface - Synchronous Mode: • Updated/Changed MIN value for PARAMETER NO. 1, tc(CLK), Cycle time, output clock GPMC_CLK period from "16" to "20" ns Section 8.8.2 • (1) "Sync mode =" footnote: GPMC Electrical Data/Timing – Deleted "Async Mode value = 125 MHz [was in Synchronous Mode section] – Updated/Changed the Sync Mode value from "62.5" to "50" MHz – Updated/Changed the Sync mode footnote to read as follows: "Sync mode can operate at 50 MHz max." Table 8-34, Timing Requirements for GPMC/NOR Flash Interface - Asynchronous Mode: • Added "The internal GPMC_FCLK is equal to SYSCLK6, ..." footnote Section 8.9.1.1 Figure 8-37, HDMI Interface High-Level Schematic: HDMI Interface • Added HDMI_HPDET signal Schematic Table 8-50, DDR-Related Control Module Registers: Section 8.13 • Added the HEX ADDRESS RANGE locations for the DDR-Related Control Module Registers LPDDR/DDR2/DDR3 Memory Controller Table 8-116, Switching Characteristics Over Recommended Operating Conditions for USB2.0: • Deleted the LOW SPEED MAX value of "-40" for PARAMETER NO. 10, ZDRV, Driver Output Resistance Section 8.22 Universal Serial Bus • Updated/Changed the MIN value for PARAMETER NO. 11, ZINP, Receiver Input Impedance for (USB2.0) LOW SPEED from "TBD" to "300" • Updated/Changed the MIN value PARAMETER NO. 11, ZINP, Receiver Input Impedance for FULL SPEED from "100" to "300" Figure 9-1, Device Nomenclature: Section 9.1.2 • Updated/Changed TMS = from "Prototype Device" to "Qualified Device" Device and Development- Support Tool • Added "C = Revision 3.0 (Other)" to SILICON REVISION Nomenclature • Added "S = Revision 3.0 (Video Security)" to SILICON REVISION Copyright © 2011–2012, Texas Instruments Incorporated Contents 9 Submit Documentation Feedback Product Folder Links: TMS320DM8148 TMS320DM8147 TMS320DM8146 |
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