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FAN5240 Datasheet(PDF) 11 Page - Fairchild Semiconductor |
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FAN5240 Datasheet(HTML) 11 Page - Fairchild Semiconductor |
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11 / 19 page  PRODUCT SPECIFICATION FAN5240 REV. 1.1.7 8/29/02 11 Additionally, the CPU power dissipation is also slightly reduced as it is proportional to the applied voltage squared and even slight voltage decrease translates to a measurable reduction in power dissipated. Figure 7. Effect of Active Droop on ESR The processor regulation window including transients is specified as +100mV..–50mV. To accommodate the droop, the output voltage of the converter is raised by about 30mV at no load. The converter response to the load step is shown in Figure 8. At zero load current, the output voltage is raised ~30mV above nominal value of 1.5V. When the load current increases, the output voltage droops down approximately 55mV. Due to use of Active Droop, the converter’s output voltage adaptively changes with the load current allowing better utilization of the regulation window. Figure 8. Converter response to 5A load step The current through each RSENSE resistor (ISNS) is sam- pled shortly after LDRV is turned on. That current is held for the remainder of the cycle, and then injected to produce an offset to VCORE+ through the external 1K resistor (R6 in Figure 1). This creates a voltage at the input to the error amplifier that rises with increasing current, causing the regu- lator’s output to droop as the current increases. Gate Driver section The gate control logic translates the internal PWM control signal into the MOSFET gate drive signals providing necessary amplification, level shifting and shoot-through protection. Also, it has functions that help optimize the IC performance over a wide range of operating conditions. Since MOSFET switching time can vary dramatically from type to type and with the input voltage, the gate control logic provides adaptive dead time by monitoring the gate-to- source voltages of both upper and lower MOSFETs. The lower MOSFET drive is not turned on until the gate-to- source voltage of the upper MOSFET has decreased to less than approximately 1 volt. Similarly, the upper MOSFET is not turned on until the gate-to-source voltage of the lower MOSFET has decreased to less than approximately 1 volt. This allows a wide variety of upper and lower MOSFETs to be used without a concern for simultaneous conduction, or shoot-through. There must be a low – resistance, low – inductance path between the driver pin and the MOSFET gate for the adap- tive dead-time circuit to work properly. Any delay along that path will subtract from the delay generated by the adaptive dead-time circit and a shoot-through condition may occur. Frequency Loop Compensation Due to the implemented current mode control, the modulator has a single pole response with -1 slope at frequency deter- mined by load where RO is load resistance, CO is load capacitance. For this type of modulator Type 2 compensation circuit is usually sufficient. To reduce the number of external components and simplify the design task, the PWM controller has an inter- nally compensated error amplifier. Figure 9 shows a Type 2 amplifier and its response along with the responses of a cur- rent mode modulator and of the converter. The Type 2 ampli- fier, in addition to the pole at the origin, has a zero-pole pair that causes a flat gain region at frequencies between the zero and the pole. ILOAD Vout (no droop) Vout droop ≈ ESR upper lim lower lim lower lim V ES V ES upper lim V DROOP I LOAD R DS ON () • 3R SENSE • -------------------------------------------- = (7) F PO 1 2 πR OCO ------------------------ = (8) |
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