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AZ7025RTR-E1 Datasheet(PDF) 9 Page - BCD Semiconductor Manufacturing Limited |
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AZ7025RTR-E1 Datasheet(HTML) 9 Page - BCD Semiconductor Manufacturing Limited |
9 / 13 page 9 BCD Semiconductor Manufacturing Limited VOLTAGE DETECTOR AZ70XX Data Sheet Oct. 2011 Rev. 2. 2 Figure 13. Low Voltage Indicator Figure 14. CPU Resetting Circuit 1 3 2 V CC AZ70XX OUT GND LED V CC R1 220 V CC +5V R1 3.3k 1 3 2 V CC AZ70XX OUT GND CPU V CC GND RESET C1 1 µF + Operating Diagram (Continued) Typical Applications Figure 12 is a typical timing waveform for AZ70XX. In normal steady-state operation when VCC>VDET-, the output will be in a logic high state and VOUT is dependent upon the voltage that the pull-up resistor connected to. Here is some explanations for AZ70XX's operation. 1. When the input voltage VCC falls below VDET-, the output will pull down to logic low after a delay time of tpHL. In general, at rated output current and VCC, VOUT can be pulled down to a voltage as low as within 0.4V from GND. (See the Electrical Characteristics section). The voltage level VDET- means the detect voltage. 2. The output, VOUT, will stay valid until VCC falls below the minimum operating voltage, VOPR (0.8V typical). Below minimum operating voltage, the out- put is undefined. 3. During power-up, VOUT will remain undefined until VCC rises above VOPR, at which time the output will become valid. VOUT will be in its active low state while VOPR<VCC<VDET+ (VDET+=VDET-+VHYS). VDET+ is the release voltage. VHYS means the hystere- sis voltage and is the difference voltage between the VDET+ and VDET-. 4. When VCC rises above VDET+, the output will be in its inactive state. After a delay time of tpLH, VOUT will be in its logic high state . |
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