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AOZ1022DI Datasheet(PDF) 11 Page - Alpha & Omega Semiconductors |
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AOZ1022DI Datasheet(HTML) 11 Page - Alpha & Omega Semiconductors |
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11 / 17 page  AOZ1022 Rev. 1.6 December 2010 www.aosmd.com Page 11 of 17 An easy-to-use application software which helps to design and simulate the compensation loop can be found at www.aosmd.com. Thermal Management and Layout Consideration In the AOZ1022 buck regulator circuit, high pulsing current flows through two circuit loops. The first loop starts from the input capacitors, to the VIN pin, to the LX pins, to the filter inductor, to the output capacitor and load, and then return to the input capacitor through ground. Current flows in the first loop when the high side switch is on. The second loop starts from inductor, to the output capacitors and load, to the anode of Schottky diode, to the cathode of Schottky diode. Current flows in the second loop when the low side diode is on. In PCB layout, minimizing the two loops area reduces the noise of this circuit and improves efficiency. A ground plane is strongly recommended to connect input capaci- tor, output capacitor, and PGND pin of the AOZ1022. In the AOZ1022 buck regulator circuit, the major power dissipating components are the AOZ1022 and the output inductor. The total power dissipation of converter circuit can be measured by input power minus output power. The power dissipation of inductor can be approximately calculated by output current and DCR of inductor. The actual junction temperature can be calculated with power dissipation in the AOZ1022 and thermal impedance from junction to ambient. The maximum junction temperature of AOZ1022 is 150°C, which limits the maximum load current capability. Please see the thermal de-rating curves for maximum load current of the AOZ1022 under different ambient temperature. The thermal performance of the AOZ1022 is strongly affected by the PCB layout. Extra care should be taken by users during design process to ensure that the IC will operate under the recommended environmental conditions. The AOZ1022 comes in an EPAD SO-8 package. Layout tips are listed below for the best electric and thermal performance. Figure 3 illustrates a PCB layout example of the AOZ1022. 1. The LX pins are connected to internal PFET and NFET drains. They are low resistance thermal conduction path and the most noisy switching node. Connected a large copper plane to the LX pin to help thermal dissipation. 2. Do not use thermal relief connection to the VIN and the PGND pin. Pour a maximized copper area to the PGND pin and the VIN pin to help thermal dissipation. 3. Input capacitor should be connected to the VIN pin and the PGND pin as close as possible. 4. A ground plane is preferred. If a ground plane is not used, separate PGND from AGND and connect them only at one point to avoid the PGND pin noise coupling to the AGND pin. 5. Make the current trace from LX pins to L to Co to the PGND as short as possible. 6. Pour copper plane on all unused board area and connect it to stable DC nodes, like VIN, GND or VOUT. 7. Keep sensitive signal trace far away form the LX pins. Ptotal_loss VIN IIN VO IO × – × = Pinductor_loss IO2 Rinductor 1.1 × × = Tjunction Ptotal_loss Pinductor_loss – () Θ × JA = |
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