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DM74KS112AM Datasheet(PDF) 3 Page - Fairchild Semiconductor

Part # DM74KS112AM
Description  Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flop with Preset, Clear, and Complementary Outputs
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Manufacturer  FAIRCHILD [Fairchild Semiconductor]
Direct Link  http://www.fairchildsemi.com
Logo FAIRCHILD - Fairchild Semiconductor

DM74KS112AM Datasheet(HTML) 3 Page - Fairchild Semiconductor

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Electrical Characteristics
over recommended operating free air temperature range (unless otherwise noted)
Note 6: All typicals are at VCC = 5V, TA = 25°C.
Note 7: Not more than one output should be shorted at a time, and the duration should not exceed one second. For devices, with feedback from the outputs,
where shorting the outputs to ground may cause the outputs to change logic state an equivalent test may be performed where VO = 2.125V with the minimum
and maximum limits reduced by one half from their stated values. This is very useful when using automatic test equipment.
Note 8: With all outputs OPEN, ICC is measured with the Q and Q outputs HIGH in turn. At the time of measurement the clock is grounded.
Switching Characteristics
at VCC = 5V and TA = 25°C
Symbol
Parameter
Conditions
Min
Typ
Max
Units
(Note 6)
VI
Input Clamp Voltage
VCC = Min, II = −18 mA
−1.5
V
VOH
HIGH Level
VCC = Min, IOH = Max
2.7
3.4
V
Output Voltage
VIL = Max, VIH = Min
VOL
LOW Level
VCC = Min, IOL = Max
0.35
0.5
Output Voltage
VIL = Max, VIH = Min
V
IOL = 4 mA, VCC = Min
0.25
0.4
II
Input Current @ Max
VCC = Max, VI = 7V
J, K
0.1
Input Voltage
Clear
0.3
mA
Preset
0.3
Clock
0.4
IIH
HIGH Level Input Current
VCC = Max, VI = 2.7V
J, K
20
Clear
60
µA
Preset
60
Clock
80
IIL
LOW Level Input Current
VCC = Max, VI = 0.4V
J, K
−0.4
Clear
−0.8
mA
Preset
−0.8
Clock
−0.8
IOS
Short Circuit Output Current
VCC = Max (Note 7)
−20
−100
mA
ICC
Supply Current
VCC = Max (Note 8)
4
6
mA
From (Input)
RL = 2 kΩ
Symbol
Parameter
To (Output)
CL = 15 pF
CL = 50 pF
Units
Min
Max
Min
Max
fMAX
Maximum Clock Frequency
30
25
MHz
tPLH
Propagation Delay Time
Preset to Q
20
24
ns
LOW-to-HIGH Level Output
tPHL
Propagation Delay Time
Preset to Q
20
28
ns
HIGH-to-LOW Level Output
tPLH
Propagation Delay Time
Clear to Q
20
24
ns
LOW-to-HIGH Level Output
tPHL
Propagation Delay Time
Clear to Q
20
28
ns
HIGH-to-LOW Level Output
tPLH
Propagation Delay Time
Clock to Q or Q
20
24
ns
LOW-to-HIGH Level Output
tPHL
Propagation Delay Time
Clock to Q or Q
20
28
ns
HIGH-to-LOW Level Output


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