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DM74LS109AM Datasheet(PDF) 1 Page - Fairchild Semiconductor |
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DM74LS109AM Datasheet(HTML) 1 Page - Fairchild Semiconductor |
1 / 5 page © 2000 Fairchild Semiconductor Corporation DS006368 www.fairchildsemi.com June 1986 Revised March 2000 DM74LS109A Dual Positive-Edge-Triggered J-K Flip-Flop with Preset, Clear, and Complementary Outputs General Description This device contains two independent positive-edge-trig- gered J-K flip-flops with complementary outputs. The J and K data is accepted by the flip-flop on the rising edge of the clock pulse. The triggering occurs at a voltage level and is not directly related to the transition time of the rising edge of the clock. The data on the J and K inputs may be changed while the clock is HIGH or LOW as long as setup and hold times are not violated. A low logic level on the preset or clear inputs will set or reset the outputs regard- less of the logic levels of the other inputs. Ordering Code: Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagram Function Table H = HIGH Logic Level L = LOW Logic Level X = Either LOW or HIGH Logic Level ↑ = Rising Edge of Pulse Q0 = The output logic level of Q before the indicated input conditions were established. Toggle = Each output changes to the complement of its previous level on each active transition of the clock pulse. Note 1: This configuration is nonstable; that is, it will not persist when pre- set and/or clear inputs return to their inactive (HIGH) state. Order Number Package Number Package Description DM74LS109AM M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow DM74LS109AN N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Inputs Outputs PR CLR CLK J K QQ LH X X X H L HL X X X L H L L X X X H (Note 1) H (Note 1) HH ↑ LL L H HH ↑ H L Toggle HH ↑ LH Q0 Q0 HH ↑ HH H L HH L X X Q0 Q0 |
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