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ADSP-2186KST-160 Datasheet(PDF) 4 Page - Analog Devices |
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ADSP-2186KST-160 Datasheet(HTML) 4 Page - Analog Devices |
4 / 36 page ADSP-2186 –4– REV. B where pin functionality is reconfigurable, the default state is shown in plain text; alternate functionality is shown in italics. Common-Mode Pins # Input/ Pin of Out- Name(s) Pins put Function RESET 1 I Processor Reset Input BR 1 I Bus Request Input BG 1 O Bus Grant Output BGH 1 O Bus Grant Hung Output DMS 1 O Data Memory Select Output PMS 1 O Program Memory Select Output IOMS 1 O Memory Select Output BMS 1 O Byte Memory Select Output CMS 1 O Combined Memory Select Output RD 1 O Memory Read Enable Output WR 1 O Memory Write Enable Output IRQ2/ 1 I Edge- or Level-Sensitive Interrupt Request 1 PF7 I/O Programmable I/O Pin IRQL0/ 1 I Level-Sensitive Interrupt Requests 1 PF5 I/O Programmable I/O Pin IRQL1/ 1 I Level-Sensitive Interrupt Requests 1 PF6 I/O Programmable I/O Pin IRQE/ 1 I Edge-Sensitive Interrupt Requests 1 PF4 I/O Programmable I/O Pin PF3 1 I/O Programmable I/O Pin Mode C/ 1 I Mode Select Input—Checked only During RESET PF2 I/O Programmable I/O Pin During Normal Operation Mode B/ 1 I Mode Select Input—Checked only During RESET PF1 I/O Programmable I/O Pin During Normal Operation Mode A/ 1 I Mode Select Input—Checked only During RESET PF0 I/O Programmable I/O Pin During Normal Operation CLKIN, XTAL 2 I Clock or Quartz Crystal Input CLKOUT 1 O Processor Clock Output SPORT0 5 I/O Serial Port I/O Pins SPORT1 5 I/O Serial Port I/O Pins IRQ1:0 Edge- or Level-Sensitive Interrupts, FI, FO Flag In, Flag Out 2 PWD 1 I Power-Down Control Input PWDACK 1 O Power-Down Control Output FL0, FL1, FL2 3 O Output Flags VDD 6 I Power (LQFP) GND 10 I Ground (LQFP) VDD 11 I Power (Mini-BGA) GND 20 I Ground (Mini-BGA) EZ-Port 9 I/O For Emulation Use NOTES 1Interrupt/Flag pins retain both functions concurrently. If IMASK is set to enable the corresponding interrupts, the DSP will vector to the appropriate interrupt vector address when the pin is asserted, either by external devices or set as a programmable flag. 2SPORT configuration determined by the DSP System Control Register. Soft- ware configurable. Memory Interface Pins The ADSP-2186 processor can be used in one of two modes: Full Memory Mode, which allows BDMA operation with full external overlay memory and I/O capability, or Host Mode, which allows IDMA operation with limited external addressing capabilities. The operating mode is determined by the state of the Mode C pin during RESET and cannot be changed while the processor is running. Full Memory Mode Pins (Mode C = 0) # of Input/ Pin Name Pins Output Function A13:0 14 O Address Output Pins for Pro- gram, Data, Byte and I/O Spaces D23:0 24 I/O Data I/O Pins for Program, Data, Byte and I/O Spaces (8 MSBs Are Also Used as Byte Memory Addresses) Host Mode Pins (Mode C = 1) # of Input/ Pin Name Pins Output Function IAD15:0 16 I/O IDMA Port Address/Data Bus A0 1 O Address Pin for External I/O, Program, Data, or Byte Access D23:8 16 I/O Data I/O Pins for Program, Data Byte and I/O Spaces IWR 1 I IDMA Write Enable IRD 1 I IDMA Read Enable IAL 1 I IDMA Address Latch Pin IS 1 I IDMA Select IACK 1 O IDMA Port Acknowledge In Host Mode, external peripheral addresses can be decoded using the A0, CMS, PMS, DMS, and IOMS signals. Terminating Unused Pin The following table shows the recommendations for terminating unused pins. Pin Terminations I/O Hi-Z * Pin 3-State Reset Caused Unused Name (Z) State By Configuration XTAL I I Float CLKOUT O O Float A13:1 or O (Z) Hi-Z BR, EBR Float IAD12:0 I/O (Z) Hi-Z IS Float A0 O (Z) Hi-Z BR, EBR Float D23:8 I/O (Z) Hi-Z BR, EBR Float D7 or I/O (Z) Hi-Z BR, EBR Float IWR I I High (Inactive) D6 or I/O (Z) Hi-Z BR, EBR Float IRD II BR, EBR High (Inactive) D5 or I/O (Z) Hi-Z Float IAL I I Low (Inactive) |
Similar Part No. - ADSP-2186KST-160 |
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Similar Description - ADSP-2186KST-160 |
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