TFP410

TI

PanelBus™ DIGITAL TRANSMITTER

SLDS145B − OCTOBER 2001 − REVISED MAY 2011

4

POST OFFICE BOX 655303

Terminal Functions (Continued)

TERMINAL

I/O

DESCRIPTION

NAME

NO.

I/O

DESCRIPTION

CTL3/A3/DK3

CTL2/A2/DK2

CTL1/A1/DK1

6

7

8

I

The operation of these three multifunction inputs depends on the settings of the ISEL (pin 13) and

DKEN (pin 35) inputs. All three inputs support 3.3-V CMOS signal levels and contain weak pulldown

resistors so that if left unconnected they default to all low.

inputs become the control inputs, CTL[3:1], which can be used to send additional information across

the DVI link during the blanking interval (DE = low). The CTL3 input is reserved for HDCP compliant DVI

TXs (TFP510) and the CTL[2:1] inputs are reserved for future use.

three inputs become the de-skew inputs DK[3:1], used to adjust the setup and hold times of the pixel

data inputs DATA[23:0], relative to the clock input IDCK±.

address, A[3:1].

Configuration/Programming

MSEN/PO1

11

O

is enabled or disabled. This pin has an open-drain output and is only 3.3-V tolerant. An external 5-kΩ

differential outputs. A high level indicates a powered on receiver is not detected. This function is only

valid in dc-coupled systems.

register descriptions section).

ISEL/RST

13

I

changed to their default values and are not preserved from before the reset.

BSEL/SCL

15

I

enabled or disabled. This pin is only 3.3-V tolerant.

selects 12-bit input, dual-edge input mode.

descriptions section). In this configuration, this pin has an open-drain output that requires an external

DSEL/SDA

14

I/O

This pin is only 3.3-V tolerant.

differential input clock mode (see the universal graphics controller interface modes section).

configuration, this pin has an open-drain output that requires an external 5-kΩ pullup resistor

EDGE/HTPLG

9

I

disabled. This input is 3.3-V tolerant only.

the input clock IDCK+. A low level selects the primary latch to occur on the falling edge of the input clock

IDCK+. This is the case for both single-ended and differential input clock modes.

VESA™ P&D and DFP standards). When used for hot-plug detection, this pin requires a series 1-KΩ

resistor.