W25Q128FVEIG datasheet(29/97 Pages) WINBOND

Part #	W25Q128FVEIG

Description	3V 128M-BIT SERIAL FLASH MEMORY WITH DUAL/QUAD SPI & QPI

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Manufacturer	WINBOND [Winbond]

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W25Q128FV

Publication Release Date: October 01, 2012

- 28 -

Revision D

(IO

1)

8.2 Instruction Descriptions

8.2.1

Write Enable (06h)

The Write Enable instruction (Figure 5) sets the Write Enable Latch (WEL) bit in the Status Register to a

1. The WEL bit must be set prior to every Page Program, Quad Page Program, Sector Erase, Block

Erase, Chip Erase, Write Status Register and Erase/Program Security Registers instruction. The Write

Enable instruction is entered by driving /CS low, shifting the instruction code “06h” into the Data Input (DI)

pin on the rising edge of CLK, and then driving /CS high.

/CS

CLK

DI

(IO

0)

DO

Mode 0

Mode 3

0

1

2

3

4

5

6

7

Mode 0

Mode 3

Instruction (06h)

High Impedance

/CS

CLK

Mode 0

Mode 3

0

1

Mode 0

Mode 3

IO

0

IO

1

IO

2

IO

3

06h

Instruction

Figure 5. Write Enable Instruction for SPI Mode (left) or QPI Mode (right)

8.2.2

Write Enable for Volatile Status Register (50h)

The non-volatile Status Register bits described in section 7.1 can also be written to as volatile bits. This

gives more flexibility to change the system configuration and memory protection schemes quickly without

waiting for the typical non-volatile bit write cycles or affecting the endurance of the Status Register non-

volatile bits. To write the volatile values into the Status Register bits, the Write Enable for Volatile Status

Register (50h) instruction must be issued prior to a Write Status Register (01h) instruction. Write Enable

for Volatile Status Register instruction (Figure 6) will not set the Write Enable Latch (WEL) bit, it is only

valid for the Write Status Register instruction to change the volatile Status Register bit values.

/CS

CLK

DI

(IO

0)

DO

(IO

1)

Mode 0

Mode 3

0

1

2

3

4

5

6

7

Mode 0

Mode 3

Instruction (50h)

High Impedance

/CS

CLK

Mode 0

Mode 3

0

1

Mode 0

Mode 3

IO

0

IO

1

IO

2

IO

3

50h

Instruction

Figure 6. Write Enable for Volatile Status Register Instruction for SPI Mode (left) or QPI Mode (right)

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