MPC952

ECLinPS and ECLinPS Lite

DL140 — Rev 3

5

MOTOROLA

VL = VS (Zo / Rs + Ro +Zo) = 3.0 (25/53.5) = 1.40V

At the load end the voltage will double, due to the near

unity reflection coefficient, to 2.8V. It will then increment

towards the quiescent 3.0V in steps separated by one round

trip delay (in this case 4.0ns).

Figure 4. Single versus Dual Waveforms

TIME (nS)

3.0

2.5

2.0

1.5

1.0

0.5

0

2

4

6

8

10

12

14

OutB

tD = 3.9386

OutA

tD = 3.8956

In

Since this step is well above the threshold region it will not

cause any false clock triggering, however designers may be

uncomfortable with unwanted reflections on the line. To

better match the impedances when driving multiple lines the

situation in Figure 5 should be used. In this case the series

terminating resistors are reduced such that when the parallel

combination is added to the output buffer impedance the line

impedance is perfectly matched.

Figure 5. Optimized Dual Line Termination

7

Ω

MPC952

OUTPUT

BUFFER

RS = 36Ω

ZO = 50Ω

RS = 36Ω

ZO = 50Ω

7

Ω + 36Ω k 36Ω = 50Ω k 50Ω

25

Ω = 25Ω

SPICE level output buffer models are available for

engineers who want to simulate their specific interconnect

schemes. In addition IV characteristics are in the process of

being generated to support the other board level simulators in

general use.

Power Supply Filtering

The MPC952 is a mixed analog/digital product and as

such it exhibits some sensitivities that would not necessarily

be seen on a fully digital product. Analog circuitry is naturally

susceptible to random noise, especially if this noise is seen

on the power supply pins. The MPC952 provides separate

power supplies for the output buffers (VCCO) and the internal

PLL (VCCA) of the device. The purpose of this design

technique is to try and isolate the high switching noise digital

outputs from the relatively sensitive internal analog

phase–locked loop. In a controlled environment such as an

evaluation board this level of isolation is sufficient. However,

in a digital system environment where it is more difficult to

minimize noise on the power supplies a second level of

isolation may be required. The simplest form of isolation is a

power supply filter on the VCCA pin for the MPC952.

Figure 6. Power Supply Filter

VCCA

VCC

MPC952

0.01

µF

22

µF

0.01

µF

3.3V

RS=5–15Ω

Figure 6 illustrates a typical power supply filter scheme.

The MPC952 is most susceptible to noise with spectral

content in the 1KHz to 1MHz range. Therefore the filter

should be designed to target this range. The key parameter

that needs to be met in the final filter design is the DC voltage

drop that will be seen between the VCC supply and the VCCA

pin of the MPC952. From the data sheet the IVCCA current

(the current sourced through the VCCA pin) is typically 15mA

(20mA maximum), assuming that a minimum of 3.0V must be

maintained on the VCCA pin very little DC voltage drop can

be tolerated when a 3.3V VCC supply is used. The resistor

shown in Figure 6 must have a resistance of 10–15

Ω to meet

the voltage drop criteria. The RC filter pictured will provide a

broadband filter with approximately 100:1 attenuation for

noise whose spectral content is above 20KHz. As the noise

frequency crosses the series resonant point of an individual

capacitor it’s overall impedance begins to look inductive and

thus increases with increasing frequency. The parallel

capacitor combination shown ensures that a low impedance

path to ground exists for frequencies well above the

bandwidth of the PLL.

Although the MPC952 has several design features to

minimize the susceptibility to power supply noise (isolated

power and grounds and fully differential PLL) there still may

be applications in which overall performance is being

degraded due to system power supply noise. The power

supply filter schemes discussed in this section should be

adequate to eliminate power supply noise related problems

in most designs.