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MPC951 Datasheet(PDF) 1 Page - Motorola, Inc |
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MPC951 Datasheet(HTML) 1 Page - Motorola, Inc |
1 / 13 page MOTOROLA SEMICONDUCTOR TECHNICAL DATA 1 REV 4 © Motorola, Inc. 1997 2/97 Low Voltage PLL Clock Driver The MPC950/951 are 3.3V compatible, PLL based clock driver devices targeted for high performance clock tree designs. With output frequencies of up to 180MHz and output skews of 375ps the MPC950 is ideal for the most demanding clock tree designs. The devices employ a fully differential PLL design to minimize cycle–to–cycle and long term jitter. This parameter is of significant importance when the clock driver is providing the reference clock for PLL’s on board today’s microprocessors and ASiC’s. The devices offer 9 low skew outputs, the outputs are configurable to support the clocking needs of the various high performance microprocessors. • Fully Integrated PLL • Oscillator or Crystal Reference Input • Output Frequency up to 180MHz • Outputs Disable in High Impedance • Compatible with PowerPC™, Intel and High Performance RISC Microprocessors • TQFP Packaging • Output Frequency Configurable • ±100ps Typical Cycle–to–Cycle Jitter Two selectable feedback division ratios are available on the MPC950 to provide input reference clock flexibility. The FBSEL pin will choose between a divide by 8 or a divide by 16 of the VCO frequency to be compared with the input reference to the MPC950. The internal VCO is running at either 2x or 4x the high speed output, depending on configuration, so that the input reference will be either one half, one fourth or one eighth the high speed output. The MPC951 replaces the crystal oscillator and internal feedback of the MPC950 with a differential PECL reference input and an external feedback input. These features allow for the MPC951 to be used as a zero delay, low skew fanout buffer. In addition, the external feedback allows for a wider variety of input–to–output frequency relationships. The MPC951 REF_SEL pin allows for the selection of an alternate LVCMOS input clock to be used as a test clock or to provide the reference for the PLL from an LVCMOS source. The MPC950 provides an external test clock input for scan clock distribution or system diagnostics. In addition the REF_SEL pin allows the user to select between a crystal input to an on–board oscillator for the reference or to chose a TTL level oscillator input directly. The on–board crystal oscillator requires no external components beyond a series resonant crystal. Both the MPC950 and MPC951 are fully 3.3V compatible and require no external loop filter components. All inputs accept LVCMOS or LVTTL compatible levels while the outputs provide LVCMOS levels with the capability to drive terminated 50 Ω transmission lines. Select inputs do not have internal pull–up/pull–down resistors and thus must be set externally. If the PECL_CLK inputs are not used, they can be left open. For series terminated 50 Ω lines, each of the MPC950/951 outputs can drive two traces giving the device an effective fanout of 1:18. The device is packaged in a 7x7mm 32–lead TQFP package to provide the optimum combination of board density and performance. PowerPC is a trademark of International Business Machines Corporation. Pentium is a trademark of Intel Corporation. MPC950 MPC951 LOW VOLTAGE PLL CLOCK DRIVER FA SUFFIX 32–LEAD TQFP PACKAGE CASE 873A–02 |
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