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MPC930 Datasheet(PDF) 10 Page - Motorola, Inc |
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MPC930 Datasheet(HTML) 10 Page - Motorola, Inc |
10 / 14 page MPC930 MPC931 MOTOROLA TIMING SOLUTIONS BR1333 — Rev 6 10 Although the MPC930/931 has several design features to minimize the susceptibility to power supply noise (isolated power and grounds and fully differential PLL) there still may be applications in which overall performance is being degraded due to system power supply noise. The power supply filter schemes discussed in this section should be adequate to eliminate power supply noise related problems in most designs. Using the Power Management Features of the MPC930/931 The MPC930/931 clock driver offers two different features that designers can take advantage of for managing power dissipation in their designs. The first feature allows the user to turn off outputs which drive portions of the system which may go idle in a sleep mode. The Shut_Dn pins allow for three different combinations of output shut down schemes. The schemes are summarized in the function tables in the data sheet. The MPC930/931 synchronizes the shut down signals internal to the chip and applies them in a manner which eliminates the possibility of creating runt pulse on the outputs. The device waits for the output to go into the “LOW” state prior to disabling. When the outputs are re–enabled the device waits and re–enables the output such that the transition is synchronous and in the proper phase relationship to the outputs which remained active. The Power_Dn pin offers another means of implementing power management schemes into a design. To use this feature the device must be set up in its normal operating mode with the Power_Dn pin “LOW”, in addition the user must use the internal feedback option. If the external feedback option were used the output frequency reduction would change the feedback frequency and the PLL will lose lock. When the Power_Dn pin is driven “HIGH” the MPC930/931 synchronizes the signal to the internal clock and then seemlessly reduces the frequency of the outputs by one half. The Power_Dn signal is synchronized to the slowest internal VCO clock. It waits until both VCO clocks are in the “LOW” state and then switches from the nominal speed VCO clock to the half speed VCO clock. This will in turn cause the current output pulse to stretch to reflect the reduction in output frequency. When the Power_Dn pin is brought back “LOW” the device will again wait until both of the VCO clocks are “LOW” and then switch to the nominal VCO clock. This will cause the current output pulses, and all successive pulses, to shrink to match the higher output frequency. Both the power up and power down features are illustrated in the timing diagrams of in this data sheet. Timing diagrams for both of the power management features are shown in Figure 3 and Figure 4 on page 3. Using the On–Board Crystal Oscillator The MPC930 features an on–board crystal oscillator to allow for seed clock generation as well as final distribution. The on–board oscillator is completely self contained so that the only external component required is the crystal. As the oscillator is somewhat sensitive to loading on its inputs the user is advised to mount the crystal as close to the MPC930/931 as possible to avoid any board level parasitics. To facilitate co–location surface mount crystals are recommended, but not required. The oscillator circuit is a series resonant circuit as opposed to the more common parallel resonant circuit, this eliminates the need for large on–board capacitors. Because the design is a series resonant design for the optimum frequency accuracy a series resonant crystal should be used (see specification table below). Unfortunately most off the shelf crystals are characterized in a parallel resonant mode. However a parallel resonant crystal is physically no different than a series resonant crystal, a parallel resonant crystal is simply a crystal which has been characterized in its parallel resonant mode. Therefore in the majority of cases a parallel specified crystal can be used with the MPC930 with just a minor frequency error due to the actual series resonant frequency of the parallel resonant specified crystal. Typically a parallel specified crystal used in a series resonant mode will exhibit an oscillatory frequency a few hundred ppm lower than the specified value. For most processor implement– ations a few hundred ppm translates into kHz inaccuracies, a level which does not represent a major issue. Table 4. Crystal Specifications Parameter Value Crystal Cut Fundamental AT Cut Resonance Series Resonance* Frequency Tolerance ±75ppm at 25°C Frequency/Temperature Stability ±150pm 0 to 70°C Operating Range 0 to 70 °C Shunt Capacitance 5–7pF Equivalent Series Resistance (ESR) 50 to 80 Ω Max Correlation Drive Level 100 µW Aging 5ppm/Yr (First 3 Years) * See accompanying text for series versus parallel resonant discussion. The MPC930 is a clock driver which was designed to generate outputs with programmable frequency relationships and not a synthesizer with a fixed input frequency. As a result the crystal input frequency is a function of the desired output frequency. For a design which utilizes the external feedback to the PLL the selection of the crystal frequency is straight forward; simply chose a crystal which is equal in frequency to the fed back signal. To determine the crystal required to produce the desired output frequency for an application which utilizes internal feedback the block diagram of Figure 15 should be used. The P and the M values for the MPC930/931 are also included in Figure 15. The M values can be found in the configuration tables included in this applications section. |
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