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74VHC541SJ Datasheet(PDF) 1 Page - Fairchild Semiconductor |
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74VHC541SJ Datasheet(HTML) 1 Page - Fairchild Semiconductor |
1 / 7 page © 2005 Fairchild Semiconductor Corporation DS011639 www.fairchildsemi.com August 1993 Revised May 2005 74VHC541 Octal Buffer/Line Driver with 3-STATE Outputs General Description The VHC541 is an advanced high-speed CMOS device fabricated with silicon gate CMOS technology. It achieves the high-speed operation similar to equivalent Bipolar Schottky TTL while maintaining the CMOS low power dissi- pation. The VHC541 is an octal buffer/line driver designed to be employed as memory and address drivers, clock drivers and bus oriented transmitter/receivers. This device is similar in function to the VHC244 while pro- viding flow-through architecture (inputs on opposite side from outputs). This pinout arrangement makes this device especially useful as an output port for microprocessors, allowing ease of layout and greater PC board density. An input protection circuit insures that 0V to 7V can be applied to the input pins without regard to the supply volt- age. This device can be used to interface 5V to 3V systems and two supply systems such as battery backup. This cir- cuit prevents device destruction due to mismatched supply and input voltages. Features s High Speed: tPD 3.5 ns (typ) at VCC 5V s Low power dissipation: ICC 4 PA (max) at TA 25qC s High noise immunity: VNIH VNIL 28% VCC (min) s Power down protection is provided on all inputs s Low noise: VOLP 0.9V (typ) s Pin and function compatible with 74HC541 Ordering Code: Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Pb-Free package per JEDEC J-STD-020B. Connection Diagram Pin Descriptions Logic Symbol IEEE/IEC Truth Table H HIGH Voltage Level X Immaterial L LOW Voltage Level Z High Impedance Order Number Package Number Package Description 74VHC541M M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide 74VHC541SJ M20D Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74VHC541MTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 74VHC541N N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Pin Names Descriptions OE1, OE2 3-STATE Output Enable Inputs I0 - I7 Inputs O0 - O7 3-STATE Outputs Inputs Outputs OE1 OE2 I LL H H HX X Z XH X Z LLL L |
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