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74VHC573 Datasheet(PDF) 4 Page - Fairchild Semiconductor |
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74VHC573 Datasheet(HTML) 4 Page - Fairchild Semiconductor |
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4 / 8 page  www.fairchildsemi.com 4 AC Electrical Characteristics Note 4: Parameter guaranteed by design. tOSLH |tPLH max tPLH min|; tOSHL |tPHL max tPHL min| Note 5: CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average operating current can be obtained by the equation: ICC (opr.) CPD * VCC * fIN ICC/8 (per Latch). The total CPD when n pcs. of the Latch operates can be calculated by the equation: CPD(total) 21 8n. AC Operating Requirements Symbol Parameter VCC (V) TA 25qCTA 40qC to 85qC Units Conditions Min Typ Max Min Max tPLH Propagation Delay 3.3 r 0.3 7.6 11.9 1.0 14.0 ns CL 15 pF tPHL Time (LE to On) 10.1 15.4 1.0 17.5 CL 50 pF 5.0 r 0.5 5.0 7.7 1.0 9.0 ns CL 15 pF 6.5 9.7 1.0 11.0 CL 50 pF tPLH Propagation Delay 3.3 r 0.3 7.0 11.0 1.0 13.0 ns CL 15 pF tPHL Time (D–On) 9.5 14.5 1.0 16.5 CL 50 pF 5.0 r 0.5 4.5 6.8 1.0 8.0 CL 15 pF 6.0 8.8 1.0 10.0 CL 50 pF tPZL 3-STATE Output 3.3 r 0.3 7.3 11.5 1.0 13.5 ns RL 1 k: CL 15 pF tPZH Enable Time 9.8 15.0 1.0 17.0 CL 50 pF 5.0 r 0.5 5.2 7.7 1.0 9.0 ns CL 15 pF 6.7 9.7 1.0 11.0 CL 50 pF tPLZ 3-STATE Output 3.3 r 0.3 10.7 14.5 1.0 16.5 ns RL 1 k: CL 50 pF tPHZ Disable Time 5.0 r 0.5 6.7 9.7 1.0 11.0 CL 50 pF tOSLH Output to Output Skew 3.3 r 0.3 1.5 1.5 ns (Note 4) CL 50 pF tOSHL 5.0 r 0.5 1.0 1.0 CL 50 pF CIN Input Capacitance 4 10 10 pF VCC Open COUT Output Capacitance 6 pF VCC 5.0V CPD Power Dissipation 29 pF (Note 5) Capacitance Symbol Parameter VCC (V) TA 25qCTA 40qC to 85qC Units Min Typ Max Min Max tw(H) Minimum Pulse 3.3 r 0.3 5.0 5.0 ns tw(L) Width (LE) 5.0 r 0.5 5.0 5.0 tS Minimum Setup Time 3.3 r 0.3 3.5 3.5 ns 5.0 r 0.5 3.5 3.5 tH Minimum Hold Time 3.3 r 0.3 1.5 1.5 ns 5.0 r 0.5 1.5 1.5 |
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Similar Description - 74VHC573 |
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