6

8717B–SEEPR–6/10

Atmel AT24C32D/64D

4.

Device Operation

CLOCK and DATA TRANSITIONS: The SDA pin is normally pulled high with an external device. Data on the SDA

pin may change only during SCL low time periods (refer to “Data Validity” diagram). Data changes during SCL

high periods will indicate a start or stop condition as defined below.

START CONDITION: A high-to-low transition of SDA with SCL high is a start condition which must precede any

other command (refer to “Start and Stop Definition” diagram).

STOP CONDITION: A low-to-high transition of SDA with SCL high is a stop condition. After a read sequence, the

stop command will place the EEPROM in a standby power mode (refer to “Start and Stop Definition” diagram).

ACKNOWLEDGE: All addresses and data words are serially transmitted to and from the EEPROM in 8-bit words.

The EEPROM sends a zero during the ninth clock cycle to acknowledge that it has received each word.

• Upon power-up

• After the receipt of the Stop bit and the completion of any internal operations.

SOFTWARE RESET: After an interruption in protocol, power loss or system reset, and 2-wire part can be protocol

reset by following these steps:

• Create a start bit condition

• Clock nine cycles

• Create another start bit followed by stop bit condition as shown below.

The device is ready for next communication after above steps have been completed.

Figure 4-1.

Software Reset

Start bit

Stop bit

Start bit

Dummy Clock Cycles

SCL

SDA

12

3

8

9